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MSM5205

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John Brandwood edited this page Jan 19, 2025 · 2 revisions

Datasheet: MSM5205

Overview

The ADPCM playback hardware consists of the following components:

  • ASIC (NEC gate array) containing ADPCM control logic.
  • Oki MSM5205 ADPCM decoder (1 channel).
  • Two M41464 DRAMs (64Kx4) for sample storage.

MSM5205 Pin Assignments

The MSM5205 comes in an 18-pin plastic DIP with "OKI M5205" stamped on it.

       +----v----+
    S1 |01     18| Vdd
    S2 |02     17| /XT
4B//3B |03     16| XT
    D0 |04     15| RESET
    D1 |05     14| /VCK
    D2 |06     13| T2
    D3 |07     12| T1
(N.C.) |08     11| (N.C.)
   Vss |09     10| DAOUT
       +---------+

Pin Descriptions:

  • S1: Sample rate select input (1/2).
  • S2: Sample rate select input (2/2).
  • 4B//3B: ADPCM data size. (0 = 3-bit samples; set D0=GND, 1 = 4-bit samples).
  • D3-D0: ADPCM data input.
  • XT, /XT: Clock input, typically a 384 KHz ceramic resonator. If using an external oscillator, connect it to XT and leave /XT unconnected.
  • /VCK: Output strobe triggered at the sample rate, used to latch D0-D3.
  • RESET: Hold HIGH for at least two /VCK pulses to reset the chip.
  • T1, T2: Test mode pins (T1=GND, T2=N.C.).
  • DAOUT: Analog output from internal DAC. 5Vp-p @ Vdd=+5V.

Sample Rate Selection

S1 S2
 0  0 : XT / 96
 0  1 : XT / 64
 1  0 : XT / 48
 1  1 : (Not documented)

For a 384 KHz clock source, these are 4, 6, and 8 KHz respectively.

MSM5205 Configuration

  • 4B//3B: Tied to +5V (4-bit sample format selected).
  • S1/S2: S1 tied to +5V, S2 tied to GND (internal clock divider set to 48).
  • Test mode pins: Not used.
  • ASIC: Drives XT, /RESET, and inputs /VCK. /XT is not used.

DRAM Configuration

The CPU interface to ADPCM RAM appears as a 64Kx8 array. However, to the chip, it is a 128Kx4 array. Samples can start on any nibble boundary. The sample length is always specified in byte (two-sample) units.

MSM5205 Timing

Typically, the MSM5205 is used with a 384 KHz resonator, and a divider of 48 provides an effective sample rate of exactly 8,000 Hz. The PCE implementation uses a programmable clock to enable more sample rates.

Clock Divider Table:

$180E   Divider    XT Frequency    Sample Rate (XT/48)

$00     16         96,270 Hz      2,005.46875 Hz
$01     15        102,680 Hz      2,139.166667 Hz
$02     14        110,020 Hz      2,292.083333 Hz
$03     13        118,480 Hz      2,468.333333 Hz
$04     12        128,350 Hz      2,673.958333 Hz
$05     11        140,020 Hz      2,917.083333 Hz
$06     10        154,020 Hz      3,208.75 Hz
$07      9        171,140 Hz      3,565.416667 Hz
$08      8        192,530 Hz      4,010.8375 Hz
$09      7        220,030 Hz      4,583.958333 Hz
$0A      6        256,700 Hz      5,347.916667 Hz
$0B      5        308,050 Hz      6,417.708333 Hz
$0C      4        385,050 Hz      8,021.875 Hz
$0D      3        513,400 Hz     10,695.8 Hz
$0E      2        770,100 Hz     16,043.75 Hz
$0F      1      1,540,200 Hz     32,087.5 Hz

ADPCM Format

The Oki ADPCM format is identical to the Intel/Dialogic VOX format. The sox utility supports this format and the PCE's non-standard sample rates.

Example Conversion Commands:

; Convert 8 KHz ADPCM data to WAV file
sox -r 8000 test.vox test.wav

; Convert WAV file to 32 KHz ADPCM data
sox music.wav -r 32000 music.vox

The resulting headerless VOX file can be directly included as binary data and stored in ADPCM RAM for playback.

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