HuC6280
The Hudson Soft HuC6280 is the 8-bit CPU of NEC's PC Engine console. It contains a customized version of a 65SC02 core, a timer, and sound generation hardware. The HuC6280 is referred to as "Dr. Pepper" or "DRP" by NEC-HE.
The HuC6280 contains a modified | 65C02 core which has several enhancements.
- additional instructions
- instructions to more efficiently write predefined values to the VDC (HuC6270)
- internal peripheral functions such as an interrupt controller
- a Memory Management Unit
- a timer
- an 8-bit parallel I/O port
- a Programmable Sound Generator.
The processor operates at two speeds, 1.7897725 MHz and 7.15909 MHz.
Full article: Programmable Sound Generator
The [abbr=Programmable Sound Generator]PSG[/abbr] (Programmable Sound Generator) provides 6 sound channels, which can be conveniently paired according to the functionality they provide:
0-1 - Waveform playback
Frequency modulation (channel 1 muted)
2-3 - Waveform playback only
4-5 - Waveform playback
White noise generation
Waveform playback is the most common and allows a 32 byte, 5 bit unsigned linear sample to be played back at selected frequencies. Frequency modulation takes this one step further, allowing the playback frequency to be dynamically adjusted according to a specified pattern. White noise is used to simulate percussion instruments and effects, such as explosions, by means of a pseudo-random square wave.
Alternatively, each channel can be individually switched to [abbr=Direct Digital to Analog converter]Direct D/A[/abbr] mode in which the programmer can send data directly to the sound mixer, allowing more complex sound patterns to be generated, such as speech. Inevitably, this requires more programming effort and CPU time.
The HuC6280 has a 64 KB logical address space and a 2 MB physical address space. To access this entire memory space, the HuC6280 uses an MMU (Memory Management Unit) that splits the memory space into a 8 KB page. The logical address space is split as follows:
Each logical 8 KB page (or page) is associated with an 8-bit register ([abbr=Mapped Page Register]MPR[/abbr]0-7) (Mapped Page Register) that contains the index of the 8 KB page in physical memory to map in this page.
The HuC6280 can address 21 bits (2 MB) of physical memory but uses 16-bit logical addresses (e.g. [tt]LDA $8020[/tt]). The 64KB logical address space is split into eight 8 KB pages. The location within this pages is defined by the lower 13 bits of the logical address. The remaining upper three bits are are used to select the [abbr=Mapped Page Register]MPR[/abbr]. Each 8KB pages (of the 64KB logical addressing space) has a corresponding 8-bit [abbr=Mapped Page Register]MPR[/abbr] which is used to create a 21 bit (13 lower bits of logical address + 8 bits of corresponding [abbr=Mapped Page Register]MPR[/abbr]) address sent over the bus.
PhysicalAddress = (LogicalAddress [b]AND[/b] 0x1FFF) [b]OR[/b] ( [abbr=Mapped Page Register]MPR[/abbr][LogicalAddress / 0x2000] * 0x2000 )
| MPR | Logical Memory Range |
|---|---|
| 0 | $0000 - $1FFF |
| 1 | $2000 - $3FFF |
| 2 | $4000 - $5FFF |
| 3 | $6000 - $7FFF |
| 4 | $8000 - $9FFF |
| 5 | $A000 - $BFFF |
| 6 | $C000 - $DFFF |
| 7 | $E000 - $FFFF |
Only two instructions are used to access these registers:
The HuC6280's timer operates off of the 7.15909 MHz clock. This clock is first sent into a divide-by-1024 counter, and the output of the clock divider is used to decrement the timer counter register, if the timer is enabled. When the timer counter register decrements when its value is 0, the timer counter will reload with the value contained in the timer latch, and the timer's IRQ line is activated. The timer's IRQ vector is located at logical address $FFFA. The timer IRQ can be acknowledged(IE the timer's IRQ line made inactive again to prevent future interrupts) by reading from the IRQ mask register, or writing to the read-only IRQ status register.
| Address(in I/O page) | R/W | Bits | Description |
|---|---|---|---|
| $0C00 | R | Bit 0 - 6 | Current timer counter value. |
| Bit 7 | (Undefined, I/O data buffer D7) | ||
| W | Bit 0 - 6 | Timer latch value. | |
| Bit 7 | Unused | ||
| $0C01 | W | Bit 0 | Timer enabled if set to 1. Writing 0, then 1, will force a reload of the timer counter from the timer latch and reset the divide-by-1024 counter. |
| Bit 1 - 7 | Unused |
| Pin | Signal | Direction | Description |
|---|---|---|---|
| 1 | A5 | out | Address bus, bit 5 |
| 2 | A4 | out | Address bus, bit 4 |
| 3 | A3 | out | Address bus, bit 3 |
| 4 | A2 | out | Address bus, bit 2 |
| 5 | A1 | out | Address bus, bit 1 |
| 6 | A0 | out | Address bus, bit 0 |
| 7 | GND | s | Ground (VSS1) |
| 8 | +5V | s | Power Supply (VAA) |
| 9 | XOUT | out | Follows XIN polarity (different pulse shape)[br](Not Connected on PC Engine) |
| 10 | XIN | in | 21.477270 MHz clock input (OSC1) |
| 11 | [o]RESET[/o] | in | Reset signal input |
| 12 | RDY | in | Induce wait state while pulled low |
| 13 | SX | out | Complementary CPU clock output [br](1 = 7.15909, 0 = 1.7897725 MHz) |
| 14 | HSM | out | High Speed Mode [br](1 = 7.15909, 0 = 1.7897725 MHz) |
| 15 | +5V | s | Power Supply (VPDD) |
| 16 | GND | s | Ground (VSS5) |
| 17 | LOUT | out | Audio output, Left channel |
| 18 | ROUT | out | Audio output, Right channel |
| 19 | +5V | s | Audio Power (VPPA) |
| 20 | +2.5V | s | Power Supply (VEE) |
| 21 | AGND | s | Ground |
| 22 | K0 | in | Input port, bit 0 (@FF:1000) |
| 23 | out | Unknown/Undocumented (combination of SX, BSY, A0?)[br](Not Connected on PC Engine) | |
| 24 | K1 | in | Input port, bit 1 (@FF:1000) |
| 25 | K2 | in | Input port, bit 2 (@FF:1000) |
| 26 | K3 | in | Input port, bit 3 (@FF:1000) |
| 27 | K4 | in | Input port, bit 4 (@FF:1000) |
| 28 | K5 | in | Input port, bit 5 (@FF:1000) |
| 29 | K6 | in | Input port, bit 6 (@FF:1000) |
| 30 | K7 | in | Input port, bit 7 (@FF:1000) |
| 31 | O0 | out | Output port, bit 0 (@FF:1000) |
| 32 | O1 | out | Output port, bit 1 (@FF:1000) |
| 33 | O2 | out | Output port, bit 2 (@FF:1000) |
| 34 | O3 | out | Output port, bit 3 (@FF:1000) |
| 35 | O4 | out | Output port, bit 4 (@FF:1000) |
| 36 | O5 | out | Output port, bit 5 (@FF:1000) |
| 37 | O6 | out | Output port, bit 6 (@FF:1000) |
| 38 | O7 | out | Output port, bit 7 (@FF:1000) |
| 39 | [o]EAT[/o] | out | Not Connected on PC Engine |
| 40 | [o]EA3[/o] | out | Not Connected on PC Engine |
| 41 | [o]EA2[/o] | out | Not Connected on PC Engine |
| 42 | [o]EA1[/o] | out | Not Connected on PC Engine |
| 43 | [o]IRQ2[/o] | in | [o]IRQ2[/o] interrupt input |
| 44 | [o]IRQ1[/o] | in | [o]IRQ1[/o] interrupt input |
| 45 | [o]NMI[/o] | in | [o]NMI[/o] interrupt input |
| 46 | SYNC | out | Memory read type; [br](1 = Opcode fetch, 0 = Not opcode fetch) |
| 47 | +5V | s | Power Supply (VDD) |
| 48 | GND | s | Ground (VSS4) |
| 49 | D0 | in / out | Data bus, bit 0 |
| 50 | D1 | in / out | Data bus, bit 1 |
| 51 | D2 | in / out | Data bus, bit 2 |
| 52 | D3 | in / out | Data bus, bit 3 |
| 53 | D4 | in / out | Data bus, bit 4 |
| 54 | D5 | in / out | Data bus, bit 5 |
| 55 | D6 | in / out | Data bus, bit 6 |
| 56 | D7 | in / out | Data bus, bit 7 |
| 57 | +5V | s | Power supply (VCC) |
| 58 | GND | s | Ground |
| 59 | [o]CEK[/o] | out | HuC6260 [o]CS[/o] (@ FF:0400-0700) |
| 60 | [o]CE7[/o] | out | HuC6270 [o]CS[/o] (@ FF:0000-03FF) |
| 61 | [o]CER[/o] | out | Work RAM [o]CS[/o] (@ F8:0000-1F00) |
| 62 | [o]RD[/o] | out | Memory read strobe |
| 63 | [o]WR[/o] | out | Memory write strobe |
| 64 | A20 | out | Address bus, bit 20 |
| 65 | A19 | out | Address bus, bit 19 |
| 66 | A18 | out | Address bus, bit 18 |
| 67 | A17 | out | Address bus, bit 17 |
| 68 | A16 | out | Address bus, bit 16 |
| 69 | A15 | out | Address bus, bit 15 |
| 70 | A14 | out | Address bus, bit 14 |
| 71 | A13 | out | Address bus, bit 13 |
| 72 | A12 | out | Address bus, bit 12 |
| 73 | A11 | out | Address bus, bit 11 |
| 74 | A10 | out | Address bus, bit 10 |
| 75 | GND | s | Ground (VSS2) |
| 76 | +5V | s | Power Supply (VBB) |
| 77 | A9 | out | Address bus, bit 9 |
| 78 | A8 | out | Address bus, bit 8 |
| 79 | A7 | out | Address bus, bit 7 |
| 80 | A6 | out | Address bus, bit 6 |