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Issues: ericsonj/verilog-format

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26 Open 5 Closed
26 Open 5 Closed
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Issues list

Formatting error when nesting if-else
#37 opened May 1, 2024 by YesSanSan
Could it support systemverilog?
#36 opened Apr 8, 2024 by wuch10
It dosen't work totally
#33 opened Apr 22, 2023 by cannotgetaname
var. name who start with "if" will cause mistake
#32 opened Apr 7, 2023 by andythebreaker
Incorrect formatting with multiple modules
#31 opened Jan 28, 2023 by lsmolinski
Incorrect formatting and lost comments for module without braces
#28 opened Dec 22, 2022 by raffaeler
indents the second module in a file (with fix)
#27 opened Nov 9, 2022 by floyd-lewis
does not indent the fork join block (includes fix)
#26 opened Nov 5, 2022 by floyd-lewis
grammar file
#23 opened Jul 20, 2022 by quantrpeter
Odd formatting for end else begin
#22 opened Jan 3, 2022 by Suhail
how to actually activate formatting?
#21 opened Dec 29, 2021 by ArcSpecter
1
pipeline
#19 opened Oct 14, 2021 by quantrpeter
1
/bin folder should be updated
#18 opened Jul 16, 2021 by HuaHuaY
if statement without end
#15 opened Jan 8, 2021 by camrbuss
Chinese Encoding / Decoding Bug
#14 opened Nov 25, 2020 by z0gSh1u
2
local variabels is piled up for parameter less modules
#13 opened Mar 25, 2020 by giothub-StefanTH
1
Comment lines should be left untouched
#12 opened Mar 25, 2020 by giothub-StefanTH
How to align multiple modules in one file?
#10 opened Mar 20, 2020 by duskmoon314
Better support for package_import_declaration in the module_ansi_header
#9 opened Aug 14, 2019 by pdonahue-ventana
case bug with parameter
#8 opened May 21, 2019 by YunKaiSu
1
Feature: align instance brackets
#7 opened Apr 16, 2019 by kdurant
Why doesn' it work ？
#6 opened Apr 12, 2019 by bmVisionEE
begin end bug
#5 opened Apr 6, 2019 by wangzhankun
always block format
#4 opened Apr 6, 2019 by wangzhankun
indentation in module with tasks
#3 opened Mar 29, 2019 by kazarynau
ProTip! Follow long discussions with comments:>50.