Incorrect formatting with multiple modules

[lsmolinski]

Too many tabs with the next formatted module. Tab increment every module.

Input file:

module FlipFlop(data,start,clk,qPrim)
input data;
input start;
input clk;
output qPrim;
reg q;
always @ ( posedge clk)
begin
case({start, data, q})
3'b000: q <= 1'b0;
3'b001: q <= 1'b0;
3'b010: q <= 1'b0;
3'b011: q <= 1'b0;
3'b100: q <= 1'b0;
3'b101: q <= 1'b1;
3'b110: q <= 1'b1;
3'b111: q <= 1'b1;
default: q <= 1'b1;
endcase
end
assign qPrim = q;
endmodule
module ControlMemory(adr_in,clk,en,data_out)
input [2-1:0] adr_in;
input clk;
input en;
output [5-1:0] data_out;
wire [2-1:0] adr_in;
reg [5-1:0] data_out;
always @ ( posedge clk)
begin
if(en)
begin
case(adr_in)
2'b00: data_out <= 5'b01110;
2'b01: data_out <= 5'b11111;
2'b10: data_out <= 5'b00111;
default: data_out <= 5'bXXXXX;
endcase
end
end
endmodule
module Counter(load,clk,start,data_in,data_out)
input load;
input clk;
input start;
input [2-1:0] data_in;
output [2-1:0] data_out;
reg [2-1:0] tmp;
initial
begin
tmp = 2'b00;
end
always @ ( posedge clk)
begin
if(~start)
begin
tmp <= 2'b00;
end
else if(load)
tmp <= data_in;
else
tmp <= tmp + 1'b1;
end
assign data_out = tmp;
endmodule
module Register(data_in,start,clk,load,data_out)
input [2-1:0] data_in;
input start;
input clk;
input load;
output [2-1:0] data_out;
reg [2-1:0] data_out;
initial
begin
data_out = 2'b00;
end
always @ ( posedge clk)
begin
if(~start)
data_out <= 2'b00;
else if(load)
data_out <= data_in;
end
endmodule
module CombinationalCircuit(x,data_in,data_out_phi,data_out_psi)
input x;
input [2-1:0] data_in;
output [2-1:0] data_out_phi;
output [2-1:0] data_out_psi;
assign data_out_phi[0] = 0;
assign data_out_phi[1] = 0;
assign data_out_psi[0] = 0;
assign data_out_psi[1] = 0;
endmodule
module CMCU(X,Start,Clock,Clock2,Y,yE)
input X;
input Start;
input Clock;
input Clock2;
output [3-1:0] Y;
output yE;
wire X;
wire Start;
wire Clock;
wire Clock2;
wire [2-1:0] tauSmall;
wire [2-1:0] Psi;
wire [2-1:0] Phi;
wire [2-1:0] Tau;
wire y0;
wire yETmp;
CombinationalCircuit CC0(X,tauSmall,Phi,Psi);
Register R0(Psi,Start,Clock,y0,tauSmall);
Counter CT0(y0,Clock,Start,Phi,Tau);
ControlMemory CM(Tau,Clock2,~yE,{Y,y0,yETmp});
FlipFlop FF0(yETmp,Start,Clock,yE);
endmodule

outputfile:

module FlipFlop(data,
                start,
                clk,
                qPrim);
    input data;
    input start;
    input clk;
    output qPrim;
    reg q;
    always @ (posedge clk)
    begin
        case({start, data, q})
            3'b000: q  <= 1'b0;
            3'b001: q  <= 1'b0;
            3'b010: q  <= 1'b0;
            3'b011: q  <= 1'b0;
            3'b100: q  <= 1'b0;
            3'b101: q  <= 1'b1;
            3'b110: q  <= 1'b1;
            3'b111: q  <= 1'b1;
            default: q <= 1'b1;
        endcase
    end
    assign qPrim = q;
endmodule
    module ControlMemory(adr_in,clk,en,data_out);
        input [2-1:0] adr_in;
        input clk;
        input en;
        output [5-1:0] data_out;
        wire [2-1:0] adr_in;
        reg [5-1:0] data_out;
        always @ (posedge clk)
        begin
            if (en)
            begin
                case(adr_in)
                    2'b00: data_out   <= 5'b01110;
                    2'b01: data_out   <= 5'b11111;
                    2'b10: data_out   <= 5'b00111;
                    default: data_out <= 5'bXXXXX;
                endcase
            end
        end
    endmodule
        module Counter(load,clk,start,data_in,data_out);
            input load;
            input clk;
            input start;
            input [2-1:0] data_in;
            output [2-1:0] data_out;
            reg [2-1:0] tmp;
            initial
            begin
                tmp = 2'b00;
            end
            always @ (posedge clk)
            begin
                if (~start)
                begin
                    tmp <= 2'b00;
                end
                else if (load)
                    tmp <= data_in;
                else
                    tmp <= tmp + 1'b1;
            end
            assign data_out = tmp;
        endmodule
            module Register(data_in,start,clk,load,data_out);
                input [2-1:0] data_in;
                input start;
                input clk;
                input load;
                output [2-1:0] data_out;
                reg [2-1:0] data_out;
                initial
                begin
                    data_out = 2'b00;
                end
                always @ (posedge clk)
                begin
                    if (~start)
                        data_out <= 2'b00;
                    else if (load)
                        data_out <= data_in;
                        end
                        endmodule
                        module CombinationalCircuit(x,data_in,data_out_phi,data_out_psi);
                            input x;
                            input [2-1:0] data_in;
                            output [2-1:0] data_out_phi;
                            output [2-1:0] data_out_psi;
                            assign data_out_phi[0] = 0;
                            assign data_out_phi[1] = 0;
                            assign data_out_psi[0] = 0;
                            assign data_out_psi[1] = 0;
                        endmodule
                            module CMCU(X,Start,Clock,Clock2,Y,yE)
                                input X;
                                input Start;
                                input Clock;
                                input Clock2;
                                output [3-1:0] Y;
                                output yE;
                                wire X;
                                wire Start;
                                wire Clock;
                                wire Clock2;
                                wire [2-1:0] tauSmall;
                                wire [2-1:0] Psi;
                                wire [2-1:0] Phi;
                                wire [2-1:0] Tau;
                                wire y0;
                                wire yETmp;
                                CombinationalCircuit CC0(X,tauSmall,Phi,Psi);
                                Register R0(Psi,Start,Clock,y0,tauSmall);
                                Counter CT0(y0,Clock,Start,Phi,Tau);
                                ControlMemory CM(Tau,Clock2,~yE,{Y,y0,yETmp});
                                FlipFlop FF0(yETmp,Start,Clock,yE);
                            endmodule