Implementation of AES-256 encryption/decryption in SystemVerilog. Validation hardware will be the TUL PYNQ Z2 board.
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Implementation of AES-256 encryption/decryption in SystemVerilog. Validation hardware will be the TUL PYNQ Z2 board.
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dzemildzigal/AES-256-SystemVerilog
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Implementation of AES-256 encryption/decryption in SystemVerilog. Validation hardware will be the TUL PYNQ Z2 board.
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