vivado.jou

#-----------------------------------------------------------
# Vivado v2024.1 (64-bit)
# SW Build 5076996 on Wed May 22 18:37:14 MDT 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
# Start of session at: Mon Oct 28 21:09:44 2024
# Process ID: 1088
# Current directory: C:/Users/dzemi/Desktop/AES-256-SystemVerilog
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14028 C:\Users\dzemi\Desktop\AES-256-SystemVerilog\AES_VERILOG.xpr
# Log file: C:/Users/dzemi/Desktop/AES-256-SystemVerilog/vivado.log
# Journal file: C:/Users/dzemi/Desktop/AES-256-SystemVerilog\vivado.jou
# Running On        :DESKTOP-95HTTJA
# Platform          :Windows Server 2016 or Windows 10
# Operating System  :19045
# Processor Detail  :AMD Ryzen 7 2700X Eight-Core Processor         
# CPU Frequency     :3693 MHz
# CPU Physical cores:8
# CPU Logical cores :16
# Host memory       :68626 MB
# Swap memory       :10200 MB
# Total Virtual     :78827 MB
# Available Virtual :71003 MB
#-----------------------------------------------------------
start_gui
open_project C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.xpr
reset_run synth_1
launch_runs synth_1 -jobs 16
wait_on_run synth_1
launch_simulation -simset [get_filesets EncryptTB ]
open_wave_config C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg
source EncryptTestBench.tcl
run 3 ns
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add_bp {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.srcs/sources_1/new/EncryptPipelined.sv} 146
run 3 ns
current_wave_config {EncryptTestBench_behav.wcfg}
add_wave {{/EncryptTestBench/encrypt/ff_1_2}} {{/EncryptTestBench/encrypt/ff_2_3}} {{/EncryptTestBench/encrypt/ff_3_4}} {{/EncryptTestBench/encrypt/ff_4_5}} {{/EncryptTestBench/encrypt/ff_5_6}} {{/EncryptTestBench/encrypt/ff_6_7}} {{/EncryptTestBench/encrypt/ff_7_8}} {{/EncryptTestBench/encrypt/ff_8_9}} {{/EncryptTestBench/encrypt/ff_9_10}} {{/EncryptTestBench/encrypt/ff_10_11}} {{/EncryptTestBench/encrypt/ff_11_12}} {{/EncryptTestBench/encrypt/ff_12_13}} {{/EncryptTestBench/encrypt/ff_13_14}} {{/EncryptTestBench/encrypt/final_out}} 
run 3 ns
run 3 ns
add_bp {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.srcs/sources_1/new/AddRoundKey.sv} 28
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close_sim
reset_run synth_1
launch_runs synth_1 -jobs 16
wait_on_run synth_1
launch_simulation -simset [get_filesets EncryptTB ]
open_wave_config C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg
source EncryptTestBench.tcl
run 3 ns
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current_wave_config {EncryptTestBench_behav.wcfg}
add_wave {{/EncryptTestBench/encrypt/ff_1_2}} {{/EncryptTestBench/encrypt/ff_2_3}} {{/EncryptTestBench/encrypt/ff_3_4}} {{/EncryptTestBench/encrypt/ff_4_5}} {{/EncryptTestBench/encrypt/ff_5_6}} {{/EncryptTestBench/encrypt/ff_6_7}} {{/EncryptTestBench/encrypt/ff_7_8}} {{/EncryptTestBench/encrypt/ff_8_9}} {{/EncryptTestBench/encrypt/ff_9_10}} {{/EncryptTestBench/encrypt/ff_10_11}} {{/EncryptTestBench/encrypt/ff_11_12}} {{/EncryptTestBench/encrypt/ff_12_13}} {{/EncryptTestBench/encrypt/ff_13_14}} {{/EncryptTestBench/encrypt/final_out}} 
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remove_bps -file {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.srcs/sources_1/new/EncryptionRound.sv} -line 49
remove_bps -file {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.srcs/sources_1/new/EncryptionInitialRound.sv} -line 53
run 3 ns
remove_bps -file {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.srcs/sources_1/new/EncryptPipelined.sv} -line 146
run 3 ns
remove_bps -file {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.srcs/sources_1/new/AddRoundKey.sv} -line 28
run 3 ns
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save_wave_config {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg}
save_wave_config {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg}
save_wave_config {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg}
save_wave_config {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg}
save_wave_config {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg}
save_wave_config {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg}
run 3 ns
run 3 ns
run 3 ns
save_wave_config {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg}
save_wave_config {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg}
save_wave_config {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg}
save_wave_config {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg}
save_wave_config {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg}
save_wave_config {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg}
save_wave_config {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg}
save_wave_config {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg}
save_wave_config {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg}
save_wave_config {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg}
save_wave_config {C:/Users/dzemi/Desktop/AES-256-SystemVerilog/AES_VERILOG.sim/EncryptTB/EncryptTestBench_behav.wcfg}
close_sim