Improved riscv-dv CI tests #117
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Links to coverage and verification reports for this PR (#117) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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Links to coverage and verification reports for this PR (#117) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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Links to coverage and verification reports for this PR (#117) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
mkurc-ant
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Links to coverage and verification reports for this PR (#117) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Eryk Szpotanski <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
…scripts Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
…n_test in CI Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
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Links to coverage and verification reports for this PR (#117) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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LGTM |
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This PR enhances
riscv-dvCI tests by separating code generation and test execution stages. The PR enables the following tests: