Code

Improved riscv-dv CI tests#117

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tmichalak merged 9 commits intochipsalliance:mainchipsalliance/Cores-VeeR-EL2:mainfrom antmicro:riscv-dv-ciantmicro/Cores-VeeR-EL2:riscv-dv-ciCopy head branch name to clipboardOct 11, 2023

+230-39

Commits

Commits on Oct 11, 2023

• Separate code generation stage and the rest of the riscv-dv testing flow

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• Generate RISC-V DV tests

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• Store riscv-dv generated (and patched) code as CI artifacts

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• Add missing dealyed effect instruction mnemonics to riscv-dv utility scripts

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• Add printing whole trace comparison log to riscv-dv tests makefile

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• Exclude illegal and hint instruction tests using Renode from CI

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• Temporarily disable Spike and Whisper for riscv-dv illegal_instruction_test in CI

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• Bump the riscv-dv submodule

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• Reword comment injected to code

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