Bumped the riscv-dv submodule

Signed-off-by: Maciej Kurc <[email protected]>
chipsalliance · Oct 9, 2023 · 8cc4421 · 8cc4421
1 parent c9ac2cd
commit 8cc4421
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diff --git a/.gitmodules b/.gitmodules
@@ -3,7 +3,7 @@
 	url = https://github.com/picolibc/picolibc
 [submodule "third_party/riscv-dv"]
 	path = third_party/riscv-dv
-	url = https://github.com/chipsalliance/riscv-dv
+	url = https://github.com/antmicro/riscv-dv
 [submodule "third_party/cocotb"]
 	path = third_party/cocotb
 	url = https://github.com/cocotb/cocotb
diff --git a/third_party/riscv-dv b/third_party/riscv-dv
+106 −0		.github/scripts/code_fixup.py
+26 −0		.github/scripts/parse_testlist.py
+63 −0		.github/workflows/build-spike.yml
+0 −27		.github/workflows/metrics-regress.yml
+182 −0		.github/workflows/run-tests.yml
+1 −1		euvm/riscv/gen/riscv_asm_program_gen.d
+2 −2		euvm/riscv/gen/riscv_load_store_instr_lib.d
+1 −1		euvm/riscv/gen/riscv_page_table_entry.d
+12 −10		euvm/riscv/gen/riscv_privileged_common_seq.d
+4 −0		run.py
+1 −0		scripts/lib.py
+4 −0		scripts/renode_log_to_trace_csv.py
+15 −3		scripts/renode_wrapper.py
+34 −15		src/riscv_pmp_cfg.sv
+3 −3		yaml/iss.yaml
+1 −0		yaml/simulator.yaml
+7 −0		yaml/whisper.json