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bug fix for determining the Link status speed/width & Link Cap speed/width #1147

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merged 5 commits into from
Apr 17, 2024
Merged

bug fix for determining the Link status speed/width & Link Cap speed/width #1147

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b5ab962
bug fix for determining the Link status speed/width & Link Cap speed/…
ruck314 Mar 26, 2024
52a0e87
code clean up
ruck314 Mar 26, 2024
09d2689
bug fix for >8 lanes
ruck314 Mar 26, 2024
8db6a88
hiding 'advance debugging' registers in the GUI
ruck314 Mar 26, 2024
b2de7c8
swap the order of displaying LnkCap/LnkStat
ruck314 Mar 26, 2024
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157 changes: 87 additions & 70 deletions python/surf/xilinx/_AxiPciePhy.py
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Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,7 @@ def __init__(
bitSize = 16,
bitOffset = 0,
mode = 'RO',
hidden = True,
))

self.add(pr.RemoteVariable(
Expand All @@ -55,6 +56,7 @@ def __init__(
bitSize = 16,
bitOffset = 16,
mode = 'RO',
hidden = True,
))

self.add(pr.RemoteVariable(
Expand All @@ -63,6 +65,7 @@ def __init__(
bitSize = 8,
bitOffset = 0,
mode = 'RO',
hidden = True,
))

self.add(pr.RemoteVariable(
Expand All @@ -71,6 +74,7 @@ def __init__(
bitSize = 8,
bitOffset = 8,
mode = 'RO',
hidden = True,
))

self.add(pr.RemoteVariable(
Expand All @@ -79,6 +83,7 @@ def __init__(
bitSize = 8,
bitOffset = 16,
mode = 'RO',
hidden = True,
))

self.add(pr.RemoteVariable(
Expand All @@ -87,6 +92,7 @@ def __init__(
bitSize = 8,
bitOffset = 24,
mode = 'RO',
hidden = True,
))

self.add(pr.RemoteVariable(
Expand All @@ -95,6 +101,7 @@ def __init__(
bitSize = 8,
bitOffset = 0,
mode = 'RO',
hidden = True,
))

self.add(pr.RemoteVariable(
Expand All @@ -103,6 +110,7 @@ def __init__(
bitSize = 8,
bitOffset = 8,
mode = 'RO',
hidden = True,
))

self.add(pr.RemoteVariable(
Expand All @@ -111,6 +119,7 @@ def __init__(
bitSize = 8,
bitOffset = 16,
mode = 'RO',
hidden = True,
))

self.add(pr.RemoteVariable(
Expand All @@ -119,6 +128,7 @@ def __init__(
bitSize = 8,
bitOffset = 24,
mode = 'RO',
hidden = True,
))

for i in range(6):
Expand All @@ -128,6 +138,7 @@ def __init__(
bitSize = 32,
bitOffset = 0,
mode = 'RO',
hidden = (i!=0),
))

self.add(pr.RemoteVariable(
Expand All @@ -136,6 +147,7 @@ def __init__(
bitSize = 32,
bitOffset = 0,
mode = 'RO',
hidden = True,
))

self.add(pr.RemoteVariable(
Expand All @@ -160,6 +172,7 @@ def __init__(
bitSize = 32,
bitOffset = 0,
mode = 'RO',
hidden = True,
))

self.add(pr.RemoteVariable(
Expand All @@ -168,6 +181,7 @@ def __init__(
bitSize = 8,
bitOffset = 0,
mode = 'RO',
hidden = True,
))

self.add(pr.RemoteVariable(
Expand All @@ -176,6 +190,7 @@ def __init__(
bitSize = 8,
bitOffset = 0,
mode = 'RO',
hidden = True,
))

self.add(pr.RemoteVariable(
Expand All @@ -184,6 +199,7 @@ def __init__(
bitSize = 8,
bitOffset = 8,
mode = 'RO',
hidden = True,
))

self.add(pr.RemoteVariable(
Expand All @@ -192,6 +208,7 @@ def __init__(
bitSize = 8,
bitOffset = 16,
mode = 'RO',
hidden = True,
))

self.add(pr.RemoteVariable(
Expand All @@ -200,88 +217,88 @@ def __init__(
bitSize = 8,
bitOffset = 24,
mode = 'RO',
hidden = True,
))

self.add(pr.RemoteVariable(
name = 'Gen2Capable',
description = 'If set, underlying integrated block supports PCIe Gen2 speed.',
offset = 0x130,
bitSize = 1,
self.addRemoteVariables(
name = "DevSpecRegion",
description = "The memory range from offset 0x40 to 0xFF in the PCI configuration header is referred to as the 'Device Specific Region'. This area is reserved for use by the device vendor and can contain any vendor-specific configuration or control registers.",
offset = 0x40,
bitSize = 8,
bitOffset = 0,
mode = 'RO',
hidden = True,
))
base = pr.UInt,
mode = "RO",
number = 192,
stride = 1,
hidden = True,
)

self.add(pr.RemoteVariable(
name = 'Gen3Capable',
description = 'If set, underlying integrated block supports PCIe Gen3 speed.',
offset = 0x130,
bitSize = 1,
bitOffset = 3,
self.add(pr.LinkVariable(
name = 'LinkStatus',
mode = 'RO',
hidden = True,
linkedGet = self.updateLinkStatus,
dependencies = [self.CapabilitiesPointer],
hidden = True,
))

self.add(pr.RemoteVariable(
name = 'RootPortPresent',
description = 'Indicates the underlying integrated block is a Root Port when this bit is set. If set, Root Port registers are present in this interface.',
offset = 0x130,
bitSize = 1,
bitOffset = 1,
mode = 'RO',
))
speedEnum = {
0: 'UNDEFINED',
1: '2.5',
2: '5',
3: '8',
4: '16',
5: '32',
6: '64',
7: '128',
}

self.add(pr.RemoteVariable(
name = 'UpConfigCapable',
description = 'Indicates the underlying integrated block is upconfig capable when this bit is set.',
offset = 0x130,
bitSize = 1,
bitOffset = 2,
mode = 'RO',
self.add(pr.LocalVariable(
name = 'LnkCapSpeed',
mode = 'RO',
value = 0,
units = 'GT/s',
enum = speedEnum
))

self.add(pr.RemoteVariable(
name = 'LnkStaSpeed',
offset = 0x70 + 0x12,
bitSize = 4,
bitOffset = 0,
mode = 'RO',
units = 'GT/s',
enum = {
0: 'UNDEFINED',
1: '2.5',
2: '5',
3: '8',
4: '16',
5: '32',
6: '64',
}
self.add(pr.LocalVariable(
name = 'LnkCapWidth',
mode = 'RO',
value = 0,
units = 'lanes',
disp = '{:d}',
))

self.add(pr.RemoteVariable(
name = 'LnkStaWidth',
offset = 0x70 + 0x12,
bitSize = 8,
bitOffset = 4,
mode = 'RO',
units = 'lanes',
disp = '{:d}',
self.add(pr.LocalVariable(
name = 'LnkStaSpeed',
mode = 'RO',
value = 0,
units = 'GT/s',
enum = speedEnum
))

self.add(pr.RemoteVariable(
name = 'LnkCapSpeed',
offset = 0x70 + 0x30,
bitSize = 4,
bitOffset = 0,
mode = 'RO',
units = 'GT/s',
enum = {
0: 'UNDEFINED',
1: '2.5',
2: '5',
3: '8',
4: '16',
5: '32',
6: '64',
}
self.add(pr.LocalVariable(
name = 'LnkStaWidth',
mode = 'RO',
value = 0,
units = 'lanes',
disp = '{:d}',
))

def updateLinkStatus(self):
# Check if value points to the Device Specific Region
if (self.CapabilitiesPointer.value() >= 0x40):

# Go to the Capabilities Pointer offset and get the Capabilities Express Endpoint offset
offset = self.DevSpecRegion[(self.CapabilitiesPointer.value()-0x40) + 1].get()

# Capabilities Express Endpoint offset
linkCap = self.DevSpecRegion[(offset-0x40) + 0x0C].get() | (self.DevSpecRegion[(offset-0x40) + 0x0D].get() << 8)
linkStatus = self.DevSpecRegion[(offset-0x40) + 0x12].get() | (self.DevSpecRegion[(offset-0x40) + 0x13].get() << 8)

# Set the link speed and width capabilities
self.LnkCapSpeed.set( (linkCap>>0) & 0xF )
self.LnkCapWidth.set( (linkCap>>4) & 0xFF )

# Set the link speed and width status
self.LnkStaSpeed.set( (linkStatus>>0) & 0xF )
self.LnkStaWidth.set( (linkStatus>>4) & 0xFF )
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