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bug fix for determining the Link status speed/width & Link Cap speed/width #1147

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merged 5 commits into from
Apr 17, 2024

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ruck314
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@ruck314 ruck314 commented Mar 26, 2024

Description

To determine the byte offset for the Capabilities: Express (v2) Endpoint register based on the provided PCIe configuration dump, you'll need to follow the PCIe specification for parsing the configuration space, focusing on finding the correct capability structure within it. Here's a step-by-step guide to do this:

  1. Start from the PCI Configuration Space: The dump you've provided looks like the content of the PCI Express (PCIe) configuration space. This space contains a variety of information including device capabilities, status, and control settings.

  2. Identify the PCI Express Capability: Capabilities in PCI configuration space start at byte 0x34 (the Capabilities Pointer field in the standard PCI Configuration space), which points to the first capability structure in a linked list. Each capability has a format that includes an ID, a pointer to the next capability (if any), and then the capability-specific data.

  3. Look for the Express Capability ID: PCI Express capabilities have a specific Capability ID, which is 0x10 for the PCIe base specification. You'll need to follow the capability pointers starting from the pointer at 0x34 until you find a capability with the ID 0x10.

  4. Parse Through the Configuration Dump: Starting from the offset given by the Capabilities Pointer at 0x34, you'll parse through the linked list of capabilities. Each entry in this list has at least two bytes: the first byte is the Capability ID, and the second byte is the pointer to the next capability (relative to the start of the configuration space).

@ruck314 ruck314 requested a review from bengineerd March 26, 2024 17:20
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ruck314 commented Mar 26, 2024

Confirmed that this now works probably:

$ sudo lspci -s 01:00.0 -vvv
01:00.0 Signal processing controller: SLAC National Accelerator Lab TID-AIR AXI Stream DAQ PCIe card
...
...
...
        Capabilities: [70] Express (v2) Endpoint, MSI 00
                LnkCap: Port #0, Speed 8GT/s, Width x16, ASPM not supported
                LnkSta: Speed 8GT/s (ok), Width x8 (downgraded)

image

@ruck314 ruck314 merged commit 13c66e5 into pre-release Apr 17, 2024
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@ruck314 ruck314 deleted the AxiPciePhy-patch branch April 17, 2024 16:25
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2 participants