1.add spke co-sim logic; 2.update pulp_c910 dependency.

pulp-platform · Dec 29, 2023 · 520b089 · 520b089
1 parent ce42f85
commit 520b089
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Showing 12 changed files with 515 additions and 68 deletions.
diff --git a/.gitignore b/.gitignore
@@ -41,4 +41,5 @@ target/sim/vsim/work/
 
 target/xilinx/cheshire.srcs/
 target/xilinx/probes.ltx
-work-dpi/
+work-dpi/
+*.img
diff --git a/Bender.yml b/Bender.yml
@@ -33,7 +33,7 @@ dependencies:
   # soc910:                   { git: "[email protected]:nwistoff/soc910.git",                  rev: 7c218d05   }
   # register_interface:       { path: vendor/pulp_register_interface                                                  }
   # soc910:                   { path: soc910/hw/system                                                              }
-  pulp_c910:                { git: "[email protected]:nwistoff/pulp_c910.git",               rev: fd4b9fce   }
+  pulp_c910:                { git: "[email protected]:nwistoff/pulp_c910.git",               rev: fef1b0ed   }
 
 export_include_dirs:
   - hw/include
@@ -58,12 +58,18 @@ sources:
     files:
       - target/sim/models/s25fs512s.v
       - target/sim/models/24FC1025.v
-      - target/sim/src/spike.sv
       - target/sim/src/vip_cheshire_soc.sv
       - target/sim/src/tb_cheshire_pkg.sv
       - target/sim/src/fixture_cheshire_soc.sv
       - target/sim/src/tb_cheshire_soc.sv
 
+  - target: any(cosim)
+    files:
+      # - target/sim/src/dpi/util/one_counter.sv
+      # - target/sim/src/dpi/util/usage_manager.sv
+      # - target/sim/src/dpi/util/mp_fifo.sv
+      - target/sim/src/spike.sv
+
   - target: all(fpga, xilinx)
     files:
       - target/xilinx/src/fan_ctrl.sv

diff --git a/cheshire.mk b/cheshire.mk
@@ -196,7 +196,7 @@ $(dpi-library)/ariane_dpi.so: $(dpi)
 
 $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: Bender.yml ./target/sim/src/riscv-isa-sim/install/lib/libriscv.so $(dpi-library)/ariane_dpi.so
 	echo "$(VLOG_ARGS)"
-	$(BENDER) script vsim -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 -t c910 -t rtl --vlog-arg="$(VLOG_ARGS) $(questa-define)" > $@
+	$(BENDER) script vsim -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 -t c910 -t rtl -t cosim --vlog-arg="$(VLOG_ARGS) $(questa-define)" > $@
 	echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@
 
 $(CHS_ROOT)/target/sim/models:
@@ -221,7 +221,8 @@ CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl
 # Emulation #
 #############
 
-include $(CHS_ROOT)/target/xilinx/xilinx.mk
+CHS_XIL_DIR := $(CHS_ROOT)/target/xilinx
+include $(CHS_XIL_DIR)/xilinx.mk
 include $(CHS_XIL_DIR)/sim/sim.mk
 CHS_XILINX_ALL += $(CHS_XIL_DIR)/scripts/add_sources.tcl
 CHS_LINUX_IMG  += $(CHS_SW_DIR)/boot/linux-${BOARD}.gpt.bin

diff --git a/target/sim/src/dpi/sim_spike.cc b/target/sim/src/dpi/sim_spike.cc
@@ -69,6 +69,15 @@ commit_log_t sim_spike_t::tick(size_t n)
   commit_log.instr = procs[0]->get_state()->last_insn;
   commit_log.was_exception = procs[0]->get_state()->was_exception;
 
+  // c910 cosim added
+  for(int i = 0; i < 32; i++) {
+    commit_log.areg_value[i] = procs[0]->get_state()->XPR[i];
+  }
+  commit_log.mstatus_value  = procs[0]->get_state()->mstatus;
+  commit_log.mcause_value   = procs[0]->get_state()->mcause;
+  commit_log.minstret_value = procs[0]->get_state()->minstret;
+
+
   return commit_log;
 }
 

diff --git a/target/sim/src/dpi/sim_spike.h b/target/sim/src/dpi/sim_spike.h
@@ -26,6 +26,13 @@ typedef struct
   uint64_t data;
   uint32_t instr;
   char     was_exception;
+
+  // c910 cosim added
+  uint64_t areg_value [32];
+  uint64_t mstatus_value;
+  uint64_t mcause_value;
+  uint64_t minstret_value;
+
 } commit_log_t;
 
 // this class encapsulates the processors and memory in a RISC-V machine.

diff --git a/target/sim/src/dpi/spike.cc b/target/sim/src/dpi/spike.cc
@@ -125,6 +125,14 @@ extern "C" void spike_tick(commit_log_t* commit_log)
   commit_log->data = commit_log_val.data;
   commit_log->instr = commit_log_val.instr;
   commit_log->was_exception = commit_log_val.was_exception;
+
+    // c910 cosim added
+  for(int i = 0; i < 32; i++) {
+    commit_log->areg_value[i] = commit_log_val.areg_value[i];
+  }
+  commit_log->mstatus_value  = commit_log_val.mstatus_value;
+  commit_log->mcause_value   = commit_log_val.mcause_value;
+  commit_log->minstret_value = commit_log_val.minstret_value;
 }
 
 extern "C" void clint_tick()

diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv
diff --git a/target/sim/src/gen_preg.py b/target/sim/src/gen_preg.py
@@ -0,0 +1,7 @@
+#!/usr/bin/env python3
+
+# for i in range(96):
+#     print("assign preg_value[%d] = dut.gen_cva6_cores[0].gen_c910_core.i_c910_axi_wrap.cpu_sub_system_axi_i.x_rv_integration_platform.x_cpu_top.x_ct_top_0.x_ct_core.x_ct_idu_top.x_ct_idu_rf_prf_pregfile.preg%d_reg_dout;" % (i, i))
+
+for i in range(32):
+    print("assign areg_preg_idx[%d] = dut.gen_cva6_cores[0].gen_c910_core.i_c910_axi_wrap.cpu_sub_system_axi_i.x_rv_integration_platform.x_cpu_top.x_ct_top_0.x_ct_core.x_ct_idu_top.x_ct_idu_ir_rt.x_ct_idu_ir_rt_entry_reg_%d.preg;"%(i,i))
diff --git a/target/sim/src/riscv-isa-sim/riscv/encoding.h b/target/sim/src/riscv-isa-sim/riscv/encoding.h
@@ -150,11 +150,22 @@
 #define IRQ_COP      12
 #define IRQ_HOST     13
 
-#define DEFAULT_RSTVEC     0x00010000
-#define CLINT_BASE         0x02000000
-#define CLINT_SIZE         0x000c0000
-#define UART_BASE          0x10000000
-#define UART_SIZE          0x00010000
+// #define DEFAULT_RSTVEC     0x00010000
+// #define CLINT_BASE         0x02000000
+// #define CLINT_SIZE         0x000c0000
+// #define UART_BASE          0x10000000
+// #define UART_SIZE          0x00010000
+// #define EXT_IO_BASE        0x40000000
+// #define DRAM_BASE          0x80000000
+// #define DUMP_BASE          0x82000000
+// #define DUMP_SIZE          0x20000000
+
+
+#define DEFAULT_RSTVEC     0x02000000
+#define CLINT_BASE         0x02040000
+#define CLINT_SIZE         0x00040000
+#define UART_BASE          0x03002000
+#define UART_SIZE          0x00001000
 #define EXT_IO_BASE        0x40000000
 #define DRAM_BASE          0x80000000
 #define DUMP_BASE          0x82000000