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Simulating submodules still doesn't work, but it's getting closer. Run cargo test #44: Commit ca5c0b2 pushed by mmaloney-sf
May 10, 2024 17:15 53s master
master
May 10, 2024 17:15 53s
Submodules might work in Verilog output now. Run cargo test #43: Commit e8ff567 pushed by mmaloney-sf
May 10, 2024 07:33 41s master
master
May 10, 2024 07:33 41s
Add a bunch of stuff. Run cargo test #42: Commit 7afec06 pushed by mmaloney-sf
May 10, 2024 06:10 48s master
master
May 10, 2024 06:10 48s
More method stuff. Run cargo test #41: Commit 9322735 pushed by mmaloney-sf
May 10, 2024 01:21 43s master
master
May 10, 2024 01:21 43s
Clocks on regs are paths, not exprs. Run cargo test #40: Commit 593db59 pushed by mmaloney-sf
May 9, 2024 03:32 42s master
master
May 9, 2024 03:32 42s
Tweaks. Run cargo test #39: Commit efad023 pushed by mmaloney-sf
May 9, 2024 02:32 49s master
master
May 9, 2024 02:32 49s
Basic Verilog output. Run cargo test #38: Commit 935ce09 pushed by mmaloney-sf
May 9, 2024 02:08 41s master
master
May 9, 2024 02:08 41s
Basic Verilog output. Run cargo test #37: Commit bcbbe67 pushed by mmaloney-sf
May 9, 2024 02:05 33s master
master
May 9, 2024 02:05 33s
Update specs. Run cargo test #36: Commit 9144805 pushed by mmaloney-sf
May 8, 2024 15:23 45s master
master
May 8, 2024 15:23 45s
Add sll, srl, get methods, syntax tweaks, index range for Words. Run cargo test #35: Commit d016199 pushed by mmaloney-sf
May 8, 2024 14:43 38s master
master
May 8, 2024 14:43 38s
Progress. Run cargo test #34: Commit bc4146b pushed by mmaloney-sf
May 8, 2024 06:59 43s master
master
May 8, 2024 06:59 43s
Progress. Run cargo test #33: Commit 13ae784 pushed by mmaloney-sf
May 8, 2024 06:40 41s master
master
May 8, 2024 06:40 41s
Tweak vim keywords. Run cargo test #32: Commit 2511884 pushed by mmaloney-sf
May 8, 2024 06:25 50s master
master
May 8, 2024 06:25 50s
A few checks on items and submodules. Run cargo test #31: Commit bb96c34 pushed by mmaloney-sf
May 8, 2024 06:22 53s master
master
May 8, 2024 06:22 53s
Split checker.rs into db.rs and several submodules. Run cargo test #30: Commit 23ece24 pushed by mmaloney-sf
May 8, 2024 05:45 45s master
master
May 8, 2024 05:45 45s
Split up salsa queries into manageable groups. Run cargo test #29: Commit 5ee8cfc pushed by mmaloney-sf
May 4, 2024 03:33 40s master
master
May 4, 2024 03:33 40s
Add cat and indexing. Run cargo test #28: Commit 371386c pushed by mmaloney-sf
May 3, 2024 17:18 43s master
master
May 3, 2024 17:18 43s
Add cat and indexing. Run cargo test #27: Commit 7482d85 pushed by mmaloney-sf
May 3, 2024 17:17 41s master
master
May 3, 2024 17:17 41s
Submodules query. Run cargo test #26: Commit c9af163 pushed by mmaloney-sf
May 3, 2024 08:22 45s master
master
May 3, 2024 08:22 45s
Submodules query. Run cargo test #25: Commit 8e39559 pushed by mmaloney-sf
May 3, 2024 08:21 50s master
master
May 3, 2024 08:21 50s
Add submodule keyword. Run cargo test #24: Commit 48f54b3 pushed by mmaloney-sf
May 3, 2024 07:30 40s master
master
May 3, 2024 07:30 40s
Slightly better elaboration. Run cargo test #23: Commit e925265 pushed by mmaloney-sf
May 3, 2024 07:29 37s master
master
May 3, 2024 07:29 37s
Tweak grammar for method calls to avoid the need for extra parens. Run cargo test #22: Commit a918fcf pushed by mmaloney-sf
May 3, 2024 06:02 45s master
master
May 3, 2024 06:02 45s
Remove some dead code. Run cargo test #21: Commit 4f5b85f pushed by mmaloney-sf
May 3, 2024 05:55 42s master
master
May 3, 2024 05:55 42s
Create Sim from a design. Run cargo test #20: Commit a73ca62 pushed by mmaloney-sf
May 3, 2024 05:49 46s master
master
May 3, 2024 05:49 46s