Clocks on regs are paths, not exprs.

src/ast.rs

@@ -35,7 +35,7 @@ pub struct Component {
     pub kind: ComponentKind,
     pub typ: Type,
     pub connect: Option<InlineConnect>,
-    pub clock: Option<Expr>,
+    pub clock: Option<Path>,
     pub reset: Option<Expr>,
 }
 

src/db/structureq.rs

@@ -40,7 +40,7 @@ fn moddef_component_hir(db: &dyn StructureQ, moddef: Ident, component: Ident) ->
         ast::ComponentKind::Reg => {
             let ast::InlineConnect(_connect_type, expr) = db.moddef_component_connects(moddef.clone(), component.clone())?[0].clone();
             let expr = hir::Expr::from_ast(&expr);
-            let clock: hir::Expr = hir::Expr::from_ast(&c.clock.unwrap());
+            let clock = c.clock.ok_or_else(|| VirdantError::Other(format!("No \"on\" clause for reg")))?;
             hir::Component::Reg(c.name.clone(), Type::from_ast(&c.typ), clock, expr)
         },
     })

src/db/typecheckq.rs

@@ -33,11 +33,10 @@ fn moddef_component_hir_typed(db: &dyn TypecheckQ, moddef: Ident, component: Ide
         },
         ast::ComponentKind::Reg => {
             let ctx = db.moddef_context(moddef.clone())?;
-            let clock: hir::Expr = hir::Expr::from_ast(&c.clock.unwrap());
-            let clock_typed: hir::Expr = clock.typecheck(ctx, Type::from_ast(&ast::Type::Clock)).map_err(|e| VirdantError::TypeError(e))?;
+            let clock = c.clock.ok_or_else(|| VirdantError::Other(format!("No \"on\" clause for reg")))?;
 
             let expr = db.typecheck_component(moddef.clone(), component.clone())?;
-            hir::Component::Reg(c.name.clone(), Type::from_ast(&c.typ), clock_typed, expr)
+            hir::Component::Reg(c.name.clone(), Type::from_ast(&c.typ), clock, expr)
         },
     })
 }

src/grammar.lalrpop

@@ -72,14 +72,14 @@ Component: Component = {
             reset: None,
         }
     },
-    "reg" <name:Id> ":" <typ:Type> "on" <clock:Expr> <rst:("reset" Expr)?> <connect:InlineConnect?> => {
+    "reg" <name:Id> ":" <typ:Type> "on" <clock:Path> <rst:("reset" Expr)?> <connect:InlineConnect?> => {
         let reset = rst.map(|s| *s.1); // .1 ignores the "reset" keyword
         Component {
             kind: ComponentKind::Reg,
             name,
             typ: *typ,
             connect,
-            clock: Some(*clock),
+            clock: Some(clock),
             reset,
         }
     },

src/hir.rs

@@ -28,14 +28,15 @@ pub struct ModDef {
 pub struct Submodule {
     pub name: Ident,
     pub moddef: Ident,
+//    pub incoming_port_connects: Vec<Connect>, // TODO
 }
 
 #[derive(Debug, Clone, PartialEq, Eq)]
 pub enum Component {
     Incoming(Ident, Arc<Type>),
     Outgoing(Ident, Arc<Type>, Expr),
     Wire(Ident, Arc<Type>, Expr),
-    Reg(Ident, Arc<Type>, Expr, /*Option<Value>,*/ Expr),
+    Reg(Ident, Arc<Type>, Path, /*Option<Value>,*/ Expr),
 }
 
 #[derive(Debug, Clone, PartialEq, Eq)]

src/mlir.rs

@@ -62,9 +62,8 @@ impl<'a> Mlir<'a> {
                 writeln!(self.writer)?;
             },
             Component::Reg(name, typ, clk, /* rst, */ expr) => {
-                let clock_ssa = self.mlir_expr(clk)?;
                 let connect_ssa = self.mlir_expr(&expr)?;
-                write!(self.writer, "    %{name} = virdant.reg({clock_ssa}, {connect_ssa}) : ")?;
+                write!(self.writer, "    %{name} = virdant.reg(%{clk}, {connect_ssa}) : ")?;
                 self.mlir_type(typ.clone())?;
                 writeln!(self.writer)?;
             },

src/sim.rs

@@ -51,7 +51,7 @@ impl SimBuilder {
         self
     }
 
-    pub fn add_reg_node(mut self, path: Path, typ: Arc<Type>, clock: Expr, reset: Option<Value>, expr: Expr) -> Self {
+    pub fn add_reg_node(mut self, path: Path, typ: Arc<Type>, clock: Path, reset: Option<Value>, expr: Expr) -> Self {
         let set_cell_id = self.sim.cells.len();
         let val_cell_id = self.sim.cells.len() + 1;
 

src/verilog.rs

@@ -111,10 +111,9 @@ impl<'a> Verilog<'a> {
                 writeln!(self.writer, "    assign {name} = {ssa};")?;
             },
             Component::Reg(name, typ, clk, /* rst, */ expr) => {
-                let clock_ssa = self.verilog_expr(clk)?;
                 let connect_ssa = self.verilog_expr(&expr)?;
                 writeln!(self.writer, "    reg  [31:0] {name};")?;
-                writeln!(self.writer, "    always @(posedge clk) begin")?;
+                writeln!(self.writer, "    always @(posedge {clk}) begin")?;
                 writeln!(self.writer, "        {name} <= {connect_ssa};")?;
                 writeln!(self.writer, "    end")?;
             },