Add a bunch of stuff.

mmaloney-sf · May 10, 2024 · 7afec06 · 7afec06
1 parent 9322735
commit 7afec06
Show file tree

Hide file tree

Showing 7 changed files with 125 additions and 36 deletions.
diff --git a/src/db/structureq.rs b/src/db/structureq.rs
@@ -15,6 +15,7 @@ pub trait StructureQ: AstQ {
     fn package_moddef_names(&self) -> VirdantResult<Vec<Ident>>;
     fn moddef_component_names(&self, moddef: Ident) -> VirdantResult<Vec<Ident>>;
     fn moddef_component_connects(&self, moddef: Ident, component: Ident) -> VirdantResult<Vec<ast::InlineConnect>>;
+    fn moddef_submodule_connects(&self, moddef: Ident, submodule: Ident) -> VirdantResult<Vec<ast::InlineConnect>>;
 
     fn check_item_names_unique(&self) -> VirdantResult<()>;
     fn check_submodule_moddefs_exist(&self) -> VirdantResult<()>;
@@ -134,6 +135,24 @@ fn moddef_component_connects(db: &dyn StructureQ, moddef: Ident, component: Iden
     Ok(result)
 }
 
+fn moddef_submodule_connects(db: &dyn StructureQ, moddef: Ident, submodule: Ident) -> Result<Vec<ast::InlineConnect>, VirdantError> {
+    let moddef_ast = db.moddef_ast(moddef)?;
+    let mut result = vec![];
+
+    for decl in &moddef_ast.decls {
+        match decl {
+            ast::Decl::Connect(ast::Connect(target, connect_type, expr)) if target.is_foreign() => {
+                if target.parts()[0] == submodule.as_str() {
+                    result.push(ast::InlineConnect(*connect_type, expr.clone()));
+                }
+
+            },
+            _ => (),
+        }
+    }
+    Ok(result)
+}
+
 fn check_item_names_unique(db: &dyn StructureQ) -> Result<(), VirdantError> {
     let mut errors = ErrorReport::new();
     let mut item_names = HashSet::new();

diff --git a/src/hir/expr/methodcall.rs b/src/hir/expr/methodcall.rs
@@ -94,7 +94,12 @@ impl IsExpr for ExprMethodCall {
 
         let result_value = match (subject_type, name.as_str()) {
             (Type::Word(1), "mux") => {
-                todo!(); // TODO
+                let c = subject_value.unwrap_word() == 1;
+                if c {
+                    arg_values[0].clone()
+                } else {
+                    arg_values[1].clone()
+                }
             },
             (Type::Word(_n), "eq") => {
                 let v = (subject_value.unwrap_word() == arg_values.first().unwrap().unwrap_word()) as u64;

diff --git a/src/lib.rs b/src/lib.rs
@@ -11,5 +11,6 @@ pub mod hir;
 pub mod db;
 pub mod common;
 pub mod elab;
+pub mod vcd;
 pub mod mlir;
 pub mod verilog;
diff --git a/src/main.rs b/src/main.rs
@@ -5,6 +5,7 @@ use virdant::hir::*;
 use virdant::common::*;
 use virdant::types::Type;
 use virdant::db;
+use virdant::vcd::Vcd;
 
 fn main() {
 //    verilog();
@@ -14,47 +15,44 @@ fn main() {
 
     let package_text = std::fs::read_to_string(filename).unwrap();
     db::compile_verilog(&package_text).unwrap();
-}
-
-pub fn sim() {
-    let package = std::fs::read_to_string("examples/sim.vir").unwrap();
 
-    let mut sim = virdant::sim::simulator(&package, "Top").unwrap();
-    println!("################################################################################");
-    println!("Initial");
-    println!("{sim}");
+//    sim(filename);
+}
 
-    sim.poke("top.r".into(), Value::Word(8, 1));
-    println!("################################################################################");
-    println!("poke top.r = 1w8");
-    println!("{sim}");
+pub fn sim(filename: &str) {
+    let package = std::fs::read_to_string(filename).unwrap();
+    let mut fout = std::fs::File::create("trace.vcd").unwrap();
 
-    sim.poke("top.in".into(), Value::Word(8, 10));
-    println!("################################################################################");
-    println!("poke top.in = 10w8");
-    println!("{sim}");
+    let mut vcd = Vcd::new(&mut fout);
+    vcd.header().unwrap();
 
-//    sim.reset();
+    let mut sim = virdant::sim::simulator(&package, "Top").unwrap();
 //    println!("################################################################################");
-//    println!("reset");
+//    println!("Initial");
 //    println!("{sim}");
 
-    sim.clock();
-    println!("################################################################################");
-    println!("clock");
-    println!("{sim}");
-
-    sim.clock();
-    println!("################################################################################");
-    println!("clock");
-    println!("{sim}");
+    let mut i = 0;
+    vcd.step(i).unwrap();
+//    vcd.val("clock", sim.peek("clock".into())).unwrap();
+    vcd.val("led_0", sim.peek("top.led_0".into())).unwrap();
+    vcd.val("led_1", sim.peek("top.led_1".into())).unwrap();
+    vcd.val("led_2", sim.peek("top.led_2".into())).unwrap();
+    vcd.val("led_3", sim.peek("top.led_3".into())).unwrap();
 
     loop {
-    sim.clock();
-    println!("################################################################################");
-    println!("clock");
-    println!("{sim}");
-    std::thread::sleep(std::time::Duration::from_millis(400));
+        i += 1;
+        sim.clock();
+//        println!("################################################################################");
+//        println!("clock");
+//        println!("{sim}");
+
+        vcd.step(i).unwrap();
+ //       vcd.val("clock", sim.peek("clock".into())).unwrap();
+        vcd.val("led_0", sim.peek("top.led_0".into())).unwrap();
+        vcd.val("led_1", sim.peek("top.led_1".into())).unwrap();
+        vcd.val("led_2", sim.peek("top.led_2".into())).unwrap();
+        vcd.val("led_3", sim.peek("top.led_3".into())).unwrap();
+//        std::thread::sleep(std::time::Duration::from_millis(400));
     }
 }
 

diff --git a/src/sim.rs b/src/sim.rs
@@ -234,6 +234,13 @@ impl Sim {
         self.flow();
     }
 
+    pub fn peek(&mut self, path: Path) -> Value {
+        let node = self.get_node(&path);
+        let cell_id = node.target_cell_id();
+        let cell = self.get_cell_mut(cell_id);
+        cell.clone()
+    }
+
     pub fn clock(&mut self) {
         let clock_id = 0; // TODO
         self.events.push(Event::Clock(clock_id));

diff --git a/src/vcd.rs b/src/vcd.rs
@@ -0,0 +1,53 @@
+use std::collections::HashMap;
+use std::io::Write;
+
+use crate::value::Value;
+use crate::types::Type;
+
+pub struct Vcd<'a> {
+    writer: &'a mut dyn Write,
+//    var_names: HashMap<String, String>,
+}
+
+impl<'a> Vcd<'a> {
+    pub fn new(writer: &'a mut dyn Write) -> Vcd<'a> {
+        Vcd { writer }
+    }
+
+    pub fn header(&mut self) -> std::io::Result<()> {
+        writeln!(self.writer, "$timescale 10ns $end")?;
+        writeln!(self.writer, "$scope module top $end")?;
+
+        writeln!(self.writer, "$var wire 1 clock clock $end")?;
+        writeln!(self.writer, "$var wire 1 led_0 led_0 $end")?;
+        writeln!(self.writer, "$var wire 1 led_1 led_1 $end")?;
+        writeln!(self.writer, "$var wire 1 led_2 led_2 $end")?;
+        writeln!(self.writer, "$var wire 1 led_3 led_3 $end")?;
+        writeln!(self.writer, "$var wire 1 pmod_0 pmod_0 $end")?;
+        writeln!(self.writer, "$upscope $end")?;
+
+        Ok(())
+    }
+
+    pub fn step(&mut self, n: usize) -> std::io::Result<()> {
+        writeln!(self.writer, "#{n}")
+    }
+
+    pub fn val(&mut self, var: &str, val: Value) -> std::io::Result<()> {
+        match val {
+            Value::Word(1, v) => write!(self.writer, "{v}")?,
+            Value::Word(w, v) => write!(self.writer, "b{v:0w$b} ", w=w as usize)?,
+            Value::X(typ) => {
+                if let Type::Word(w) = typ.as_ref() {
+                    let x_str = "x".repeat(*w as usize);
+                    write!(self.writer, "{x_str}")?;
+                } else {
+                    panic!()
+                }
+            },
+            _ => panic!(),
+        }
+        writeln!(self.writer, "{var}")?;
+        Ok(())
+    }
+}
diff --git a/src/verilog.rs b/src/verilog.rs
@@ -65,16 +65,16 @@ impl<'a> Verilog<'a> {
                     let max_bit = n - 1;
                     let width_str = format!("[{max_bit}:0]");
                     let padded_width_str = format!("{width_str: >8}");
-                    write!(self.writer, "    input  wire {padded_width_str} {name}")?;
+                    write!(self.writer, "    input  wire  {padded_width_str} {name}")?;
                 } else if let Type::Clock = typ.as_ref() {
-                    write!(self.writer, "    input  wire          {name}")?;
+                    write!(self.writer, "    input  wire            {name}")?;
                 } else {
                     todo!()
                 }
             },
             Component::Outgoing(name, typ, _expr) => {
                 if let Type::Word(1) = typ.as_ref() {
-                    write!(self.writer, "    output wire             {name}")?;
+                    write!(self.writer, "    output wire            {name}")?;
                 } else if let Type::Word(n) = typ.as_ref() {
                     let max_bit = n - 1;
                     let width_str = format!("[{max_bit}:0]");
@@ -188,6 +188,12 @@ impl<'a> Verilog<'a> {
                     "mux" => {
                         writeln!(self.writer, "    wire [31:0] {gs} = {subject_ssa} ? {};", args_ssa.join(" : "))?;
                     },
+                    "sll" => {
+                        writeln!(self.writer, "    wire [31:0] {gs} = {subject_ssa} << {};", args_ssa.join(" : "))?;
+                    },
+                    "srl" => {
+                        writeln!(self.writer, "    wire [31:0] {gs} = {subject_ssa} >> {};", args_ssa.join(" : "))?;
+                    },
                     _ => panic!("Unknown method: {}", m.method()),
                 }
                 Ok(gs)