[WIP] Uniquify top-specific FuseSoC cores and remove Darjeeling's FUSESOC_IGNORE

.github/workflows/bitstream.yml

@@ -82,11 +82,21 @@ jobs:
         if: steps.strategy.outputs.bitstreamStrategy != 'cached'
         run: |
           . util/build_consts.sh
+
+          vlnv_path=lowrisc_systems_chip_${{ inputs.top_name }}_${{ inputs.design_suffix }}_0.1
+          design_name=chip_${{ inputs.top_name }}_${{ inputs.design_suffix }}
+
           echo "Synthesis log"
-          cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/build.fpga_${{ inputs.design_suffix }}/synth-vivado/lowrisc_systems_chip_${{ inputs.top_name }}_${{ inputs.design_suffix }}_0.1.runs/synth_1/runme.log || true
+          cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/${design_name}/build.fpga_${{ inputs.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/synth_1/runme.log || true
 
           echo "Implementation log"
-          cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/build.fpga_${{ inputs.design_suffix }}/synth-vivado/lowrisc_systems_chip_${{ inputs.top_name }}_${{ inputs.design_suffix }}_0.1.runs/impl_1/runme.log || true
+          cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/${design_name}/build.fpga_${{ inputs.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/impl_1/runme.log || true
+
+          echo "Utilization report"
+          cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/${design_name}/build.fpga_${{ inputs.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/impl_1/${design_name}_utilization_placed.rpt || true
+
+          echo "Timing summary report"
+          cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/${design_name}/build.fpga_${{ inputs.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/impl_1/${design_name}_timing_summary_routed.rpt || true
 
       - name: Upload step outputs
         uses: actions/upload-artifact@v4

ci/install-package-dependencies.sh

@@ -81,8 +81,14 @@ xargs sudo $APT_CMD install -y <"$ci_reqs"
 # appropriate bin directory to the PATH
 export PATH=$HOME/.local/bin:$PATH
 
+sudo python3 -m pip uninstall fusesoc -y
 python3 -m pip install --user -r python-requirements.txt --require-hashes
 
+ls $HOME/.local/bin
+
+$HOME/.local/bin/fusesoc --version
+fusesoc --version
+
 # Install Verible
 lsb_sr="$(lsb_release -sr)"
 VERIBLE_BASE_URL="https://github.com/chipsalliance/verible/releases/download"

ci/scripts/build-chip-verilator.sh

@@ -20,13 +20,15 @@ case "$tl" in
     earlgrey)
         fileset=fileset_top
         fusesoc_core=lowrisc:dv:chip_verilator_sim
+        vlnv_path=lowrisc_dv_chip_verilator_sim_0.1
         vname=Vchip_sim_tb
         verilator_options="--threads 4"
         make_options="-j 4"
         ;;
     englishbreakfast)
         fileset=fileset_topgen
         fusesoc_core=lowrisc:systems:chip_englishbreakfast_verilator
+        vlnv_path=lowrisc_systems_chip_englishbreakfast_verilator_0.1
         vname=Vchip_englishbreakfast_verilator
         # Englishbreakfast on CI runs on a 2-core CPU
         verilator_options="--threads 2"
@@ -55,5 +57,5 @@ fusesoc --cores-root=. \
   --verilator_options="${verilator_options}" \
   --make_options="${make_options}"
 
-cp "$OBJ_DIR/hw/sim-verilator/${vname}" \
+cp "$OBJ_DIR/hw/${vlnv_path}/sim-verilator/${vname}" \
    "$BIN_DIR/hw/top_${tl}/Vchip_${tl}_verilator"

hw/BUILD

@@ -43,7 +43,7 @@ fusesoc_build(
     data = ["//hw/ip/otbn:all_files"],
     make_options = ":make_options",
     output_groups = {
-        "binary": ["sim-verilator/Vchip_sim_tb"],
+        "binary": ["lowrisc_dv_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb"],
     },
     systems = ["lowrisc:dv:chip_verilator_sim"],
     tags = [

hw/bitstream/vivado/BUILD

@@ -13,12 +13,12 @@ load("//rules:bitstreams.bzl", "bitstream_manifest_fragment")
 package(default_visibility = ["//visibility:public"])
 
 # The readmem directives in the fusesoc-ized build tree will be in the subdir
-# ${build_root}/src/lowrisc_prim_util_memload_0/rtl/prim_util_memload.svh,
+# ${build_root}/${core}/${target}-${tool}/src/lowrisc_prim_util_memload_0/rtl/prim_util_memload.svh,
 # and ${build_root} will be a subdirectory called `build.fpga_cw310` inside of
 # bazel-out/k8-{configname}/bin/hw/bitstream/vivado.
 # Therefore, the relative path between prim_util_memload.svh and the project-root
 # relative $(location ...) resolved labels is up 10 subdirectories.
-_PREFIX = "../../../../../../../../../.."
+_PREFIX = "../../../../../../../../../../.."
 
 _CW310_TESTROM = "//sw/device/lib/testing/test_rom:test_rom_fpga_cw310_scr_vmem"
 
@@ -32,6 +32,8 @@ _CW340_TESTROM_PATH = _CW310_TESTROM_PATH
 
 _OTP_RMA_PATH = "{}/$(location {})".format(_PREFIX, _OTP_RMA)
 
+_FPGA_PATH_TMPL = "lowrisc_systems_{}_0.1/synth-vivado/{}"
+
 # Note: all of the targets are tagged with "manual" to prevent them from being
 # matched by bazel wildcards like "//...".  In order to build the bitstream,
 # you need to ask for it directly or by dependency via another rule, such as
@@ -51,10 +53,10 @@ fusesoc_build(
         "--OtpCtrlMemInitFile=" + _OTP_RMA_PATH,
     ],
     output_groups = {
-        "bitstream": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_0.1.bit"],
-        "rom_mmi": ["synth-vivado/rom.mmi"],
-        "otp_mmi": ["synth-vivado/otp.mmi"],
-        "logs": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_0.1.runs/"],
+        "bitstream": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "lowrisc_systems_chip_earlgrey_cw310_0.1.bit")],
+        "rom_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "rom.mmi")],
+        "otp_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "otp.mmi")],
+        "logs": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "lowrisc_systems_chip_earlgrey_cw310_0.1.runs/")],
     },
     systems = ["lowrisc:systems:chip_earlgrey_cw310"],
     tags = ["manual"],
@@ -101,10 +103,10 @@ fusesoc_build(
         "--OtpCtrlMemInitFile=" + _OTP_RMA_PATH,
     ],
     output_groups = {
-        "bitstream": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.bit"],
-        "rom_mmi": ["synth-vivado/rom.mmi"],
-        "otp_mmi": ["synth-vivado/otp.mmi"],
-        "logs": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.runs/"],
+        "bitstream": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.bit")],
+        "rom_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "rom.mmi")],
+        "otp_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "otp.mmi")],
+        "logs": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.runs/")],
     },
     systems = ["lowrisc:systems:chip_earlgrey_cw310_hyperdebug"],
     tags = ["manual"],
@@ -151,10 +153,10 @@ fusesoc_build(
         "--OtpCtrlMemInitFile=" + _OTP_RMA_PATH,
     ],
     output_groups = {
-        "bitstream": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw340_0.1.bit"],
-        "rom_mmi": ["synth-vivado/rom.mmi"],
-        "otp_mmi": ["synth-vivado/otp.mmi"],
-        "logs": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw340_0.1.runs/"],
+        "bitstream": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "lowrisc_systems_chip_earlgrey_cw340_0.1.bit")],
+        "rom_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "rom.mmi")],
+        "otp_mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "otp.mmi")],
+        "logs": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "lowrisc_systems_chip_earlgrey_cw340_0.1.runs/")],
     },
     systems = ["lowrisc:systems:chip_earlgrey_cw340"],
     tags = ["manual"],

hw/dv/dpi/dpi_sim_cfg.hjson

@@ -10,12 +10,12 @@
   build_modes: [
     {
       name: vcs_dpi_build_opts
-      build_opts: ["-CFLAGS -I{build_dir}/src/{dpi_common_dir}", "-lutil"]
+      build_opts: ["-CFLAGS -I{build_dir}/fusesoc-work/src/{dpi_common_dir}", "-lutil"]
     }
 
     {
       name: xcelium_dpi_build_opts
-      build_opts: ["-I{build_dir}/src/{dpi_common_dir}", "-lutil"]
+      build_opts: ["-I{build_dir}/fusesoc-work/src/{dpi_common_dir}", "-lutil"]
     }
   ]
 }

hw/dv/sv/sec_cm/prim_sparse_fsm_flop_if.sv

@@ -23,7 +23,7 @@ interface prim_sparse_fsm_flop_if #(
   string msg_id = $sformatf("%m");
 
   string path = dv_utils_pkg::get_parent_hier($sformatf("%m"));
-  string signal_forced = $sformatf("%s.u_state_flop.q_o", path);
+  string signal_forced = $sformatf("%s.state_o", path);
 
   // This signal only has to be forced if the associated parameter
   // CustomForceName in prim_sparse_fsm_flop is set to a non-empty string.

hw/dv/tools/dvsim/fusesoc.hjson

@@ -8,10 +8,10 @@
                        "run",
                        "{sv_flist_gen_flags}",
                        "--target=sim",
-                       "--build-root={build_dir}",
+                       "--work-root={build_dir}/fusesoc-work",
                        "--setup {fusesoc_core}"]
   fusesoc_cores_root_dirs: ["--cores-root {proj_root}"]
-  sv_flist_gen_dir:   "{build_dir}/sim-vcs"
+  sv_flist_gen_dir:   "{build_dir}/fusesoc-work"
   sv_flist:           "{sv_flist_gen_dir}/{fusesoc_core_}.scr"
   sv_flist_gen_flags: ["--flag=fileset_{design_level}"]
 }

hw/dv/tools/dvsim/xcelium.hjson

@@ -46,7 +46,7 @@
                // Ignore warning "Include directory <path> given but not used". This is benign.
                "-nowarn SPDUSD",
                // Needed for including "secded_enc.h".
-               "-I{build_dir}/src/lowrisc_dv_secded_enc_0",
+               "-I{build_dir}/fusesoc-work/src/lowrisc_dv_secded_enc_0",
                // This warning is thrown when a scalar enum variable is assigned to an enum array.
                // Other tools (e.g., FPV) treat such assignments as an error, hence we bump it to
                // an error in simulation so that this can be caught early in CI.

hw/dv/verilator/cpp/scrambled_ecc32_mem_area.cc

@@ -117,10 +117,8 @@ std::vector<uint8_t> ScrambledEcc32MemArea::GetScrambleNonce() const {
 ScrambledEcc32MemArea::ScrambledEcc32MemArea(const std::string &scope,
                                              uint32_t size, uint32_t width_32,
                                              bool repeat_keystream)
-    : Ecc32MemArea(
-          SVScoped::join_sv_scopes(
-              scope, "u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic"),
-          size, width_32),
+    : Ecc32MemArea(SVScoped::join_sv_scopes(scope, "u_prim_ram_1p_adv.u_mem"),
+                   size, width_32),
       scr_scope_(scope) {
   addr_width_ = vbits(size);
   repeat_keystream_ = repeat_keystream;

hw/dv/verilator/memutil_dpi_scrambled_opts.hjson

@@ -24,29 +24,29 @@
   build_modes: [
     {
       name: vcs_memutil_dpi_scrambled_build_opts
-      build_opts: ["-CFLAGS -I{build_dir}/src/{memutil_dpi_src_dir}/cpp",
-                   "-CFLAGS -I{build_dir}/src/{memutil_dpi_scrambled_src_dir}/cpp",
-                   "-CFLAGS -I{build_dir}/src/{secded_enc_src_dir}",
-                   "-CFLAGS -I{build_dir}/src/{scramble_model_dir}",
-                   "-CFLAGS -I{build_dir}/src/{prince_ref_src_dir}",
+      build_opts: ["-CFLAGS -I{build_dir}/fusesoc-work/src/{memutil_dpi_src_dir}/cpp",
+                   "-CFLAGS -I{build_dir}/fusesoc-work/src/{memutil_dpi_scrambled_src_dir}/cpp",
+                   "-CFLAGS -I{build_dir}/fusesoc-work/src/{secded_enc_src_dir}",
+                   "-CFLAGS -I{build_dir}/fusesoc-work/src/{scramble_model_dir}",
+                   "-CFLAGS -I{build_dir}/fusesoc-work/src/{prince_ref_src_dir}",
                    "-lelf"]
     }
 
     {
       name: xcelium_memutil_dpi_scrambled_build_opts
-      build_opts: ["-I{build_dir}/src/{memutil_dpi_src_dir}/cpp",
-                   "-I{build_dir}/src/{memutil_dpi_scrambled_src_dir}/cpp",
-                   "-I{build_dir}/src/{prince_ref_src_dir}",
-                   "-I{build_dir}/src/{scramble_model_dir}",
+      build_opts: ["-I{build_dir}/fusesoc-work/src/{memutil_dpi_src_dir}/cpp",
+                   "-I{build_dir}/fusesoc-work/src/{memutil_dpi_scrambled_src_dir}/cpp",
+                   "-I{build_dir}/fusesoc-work/src/{prince_ref_src_dir}",
+                   "-I{build_dir}/fusesoc-work/src/{scramble_model_dir}",
                    "-lelf"]
     }
 
     {
       name: dsim_memutil_dpi_scrambled_build_opts
-      build_opts: ["-c-opts -I{build_dir}/src/{memutil_dpi_src_dir}/cpp",
-                   "-c-opts -I{build_dir}/src/{memutil_dpi_scrambled_src_dir}/cpp",
-                   "-c-opts -I{build_dir}/src/{prince_ref_src_dir}",
-                   "-c-opts -I{build_dir}/src/{scramble_model_dir}",
+      build_opts: ["-c-opts -I{build_dir}/fusesoc-work/src/{memutil_dpi_src_dir}/cpp",
+                   "-c-opts -I{build_dir}/fusesoc-work/src/{memutil_dpi_scrambled_src_dir}/cpp",
+                   "-c-opts -I{build_dir}/fusesoc-work/src/{prince_ref_src_dir}",
+                   "-c-opts -I{build_dir}/fusesoc-work/src/{scramble_model_dir}",
                    "-ld-opts -lelf"]
     }
   ]

hw/ip/adc_ctrl/dv/env/adc_ctrl_env.core

@@ -40,6 +40,7 @@ generate:
     parameters:
       name: adc_ctrl
       ip_hjson: ../../data/adc_ctrl.hjson
+    position: prepend
 
 targets:
   default:

hw/ip/aes/dv/env/aes_env.core

@@ -52,6 +52,7 @@ generate:
     parameters:
       name: aes
       ip_hjson: ../../data/aes.hjson
+    position: prepend
 
 targets:
   default:

hw/ip/aes/model/aes_model_sim_opts.hjson

@@ -10,12 +10,12 @@
   build_modes: [
     {
       name: vcs_aes_model_build_opts
-      build_opts: ["-CFLAGS -I{build_dir}/src/{aes_model_src_dir}", "-lcrypto"]
+      build_opts: ["-CFLAGS -I{build_dir}/fusesoc-work/src/{aes_model_src_dir}", "-lcrypto"]
     }
 
     {
       name: xcelium_aes_model_build_opts
-      build_opts: ["-I{build_dir}/src/{aes_model_src_dir}", "-lcrypto"]
+      build_opts: ["-I{build_dir}/fusesoc-work/src/{aes_model_src_dir}", "-lcrypto"]
     }
   ]
 }

hw/ip/aon_timer/dv/env/aon_timer_env.core

@@ -31,6 +31,7 @@ generate:
     parameters:
       name: aon_timer
       ip_hjson: ../../data/aon_timer.hjson
+    position: prepend
 
 targets:
   default:

hw/ip/csrng/dv/env/csrng_env.core

@@ -43,6 +43,7 @@ generate:
     parameters:
       name: csrng
       ip_hjson: ../../data/csrng.hjson
+    position: prepend
 
 targets:
   default:

hw/ip/edn/dv/env/edn_env.core

@@ -38,6 +38,7 @@ generate:
     parameters:
       name: edn
       ip_hjson: ../../data/edn.hjson
+    position: prepend
 
 targets:
   default:

hw/ip/entropy_src/dv/env/entropy_src_env.core

@@ -46,6 +46,7 @@ generate:
     parameters:
       name: entropy_src
       ip_hjson: ../../data/entropy_src.hjson
+    position: prepend
 
 targets:
   default:

hw/ip/entropy_src/dv/env/entropy_src_env_cfg.sv

@@ -281,7 +281,7 @@ class entropy_src_env_cfg extends cip_base_env_cfg #(.RAL_T(entropy_src_reg_bloc
        0: path = {path, ".i_sync_n"};
        1: path = {path, ".i_sync_p"};
      endcase
-     disabled_prim_cdc_rand_delays[i] = {path, ".gen_generic.u_impl_generic.u_prim_cdc_rand_delay"};
+     disabled_prim_cdc_rand_delays[i] = {path, ".u_prim_cdc_rand_delay"};
     end
   endfunction
 

hw/ip/gpio/dv/env/gpio_env.core

@@ -36,6 +36,7 @@ generate:
     parameters:
       name: gpio
       ip_hjson: ../../data/gpio.hjson
+    position: prepend
 
 targets:
   default:

hw/ip/hmac/dv/env/hmac_env.core

@@ -42,6 +42,7 @@ generate:
     parameters:
       name: hmac
       ip_hjson: ../../data/hmac.hjson
+    position: prepend
 
 targets:
   default:

hw/ip/hmac/dv/hmac_sim_cfg.hjson

@@ -95,7 +95,7 @@
       name: hmac_test_sha256_vectors
       uvm_test_seq: hmac_test_vectors_sha_vseq
       // Increase timeout for all test iterations to pass
-      run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256"]
+      run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256"]
       reseed: 5
     }
 
@@ -118,34 +118,34 @@
     {
       name: hmac_test_hmac256_vectors
       uvm_test_seq: hmac_test_vectors_hmac_vseq
-      run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256"]
+      run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256"]
       reseed: 5
     }
 
     {
       name: hmac_test_hmac384_vectors
       uvm_test_seq: hmac_test_vectors_hmac_vseq
-      run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384"]
+      run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384"]
       reseed: 5
     }
 
     {
       name: hmac_test_hmac512_vectors
       uvm_test_seq: hmac_test_vectors_hmac_vseq
-      run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512"]
+      run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512"]
       reseed: 5
     }
 
     {
       // Append the common stress_tests.hjson entry for more run_opts.
       name: hmac_stress_all
-      run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0"]
+      run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0"]
     }
 
     {
       // Append the common stress_tests.hjson entry for more run_opts.
       name: hmac_stress_all_with_rand_reset
-      run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0"]
+      run_opts: ["+test_vectors_dir={build_dir}/fusesoc-work/src/lowrisc_dv_test_vectors_0"]
       reseed: 10
     }
   ]

hw/ip/i2c/dv/env/i2c_env.core

@@ -70,6 +70,7 @@ generate:
     parameters:
       name: i2c
       ip_hjson: ../../data/i2c.hjson
+    position: prepend
 
 targets:
   default:

hw/ip/keymgr/dv/env/keymgr_env.core

@@ -45,6 +45,7 @@ generate:
     parameters:
       name: keymgr
       ip_hjson: ../../data/keymgr.hjson
+    position: prepend
 
 targets:
   default: