[top_earlgrey] Reduce number of PRINCE half rounds for main SRAM scrambling

[vogelpi]

This PR contains multiple commits to reduce the number of PRINCE half rounds for the main SRAM scrambling from 3 back to 2 as used for Earlgrey ES. This is done to reduce timing pressure.

The scrambling parameters of the other scrambled memory primitives (retention SRAM, ROM, OTBN IMEM & DMEM) are not touched by this PR.

This PR supersedes #24376 as it also includes the required tooling changes. #24376 is intentionally left untouched to allow comparing the RTL changes as #24376 has already been absorbed by the PD team last week, i.e., we must not change the RTL beyond #24376.

For reference, the PRs where we increased the number of scrambling rounds in the past are:

• [prim, rom_ctrl] Increase number of PRINCE rounds for improved security #22425
• [rv_core_ibex] Re-vendor Ibex and reduce number of PRINCE rounds for ICache scrambling #22948

[vogelpi]

CHANGE AUTHORIZED: hw/ip/sram_ctrl/data/sram_ctrl.hjson
CHANGE AUTHORIZED: hw/ip/sram_ctrl/rtl/sram_ctrl.sv
CHANGE AUTHORIZED: hw/top_earlgrey/data/top_earlgrey.hjson
CHANGE AUTHORIZED: hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

This is an ECO PR confirmed by the PD team.

[andreaskurth]

Many thanks for this well-designed and -structured PR, @vogelpi! The changes LGTM and are aligned with discussions/decisions.

Just one question: What evidence on the DV side (top- and block-level tests) do we have that this works as intended?

[andreaskurth]

To ensure there are no inadvertent changes compared to what the PD team is working with, I git diff'ed hw/ip/sram_ctrl/rtl/sram_ctrl.sv and hw/top_earlgrey/rtl/autogen/top_earlgrey.sv (which are the only RTL files changed by this PR) w.r.t. PR #24376: that diff is empty. ✔️

[andreaskurth]

CHANGE AUTHORIZED: hw/ip/sram_ctrl/data/sram_ctrl.hjson
CHANGE AUTHORIZED: hw/ip/sram_ctrl/rtl/sram_ctrl.sv
CHANGE AUTHORIZED: hw/top_earlgrey/data/top_earlgrey.hjson
CHANGE AUTHORIZED: hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

This is an ECO PR confirmed by the PD team.

[vogelpi]

Many thanks for this well-designed and -structured PR, @vogelpi! The changes LGTM and are aligned with discussions/decisions.

Just one question: What evidence on the DV side (top- and block-level tests) do we have that this works as intended?

Thanks for your review @andreaskurth . We have the following tests running in CI:

• top-level:
  • chip_sw_power_virus: does some back door accesses into the main SRAM to communicate with the C side
  • chip_sw_sram_scrambled_access: does back door accesses into all scrambled SRAMs to test the scrambling, including error generation
• block-level:
  • SRAM_CTRL_MAIN smoke test: tests the SRAM_CTRL configuration (2 half rounds) used for the main SRAM, including backdoor accesses
  • SRAM_CTRL_RET smoke test: tests the SRAM_CTRL congfiguration (3 half rounds) used for the retention SRAM, including backdoor accesses

There is also a C++ model of the scrambler hw/ip/prim/dv/prim_ram_scr/cpp/scramble_model.cc that is not touched by this PR. My understanding is that we only use this C++ model for OTBN block-level Verilator simulation. OTBN uses the default setting of 3 half rounds. This model is also run in CI.

[vogelpi]

From a security side, this has been approved already by @johannheyszl .