[sival] Improve reliability of UART baud rate test #2355

Job	Run time
Lint (quick)	2m 56s
Lint (slow)	12m 59s
Airgapped build	8m 24s
CW305's Bitstream	24m 15s
Verible lint	0s
Verilated Earl Grey	1h 3m 54s
Verilated English Breakfast	8m 32s
Build Docker Containers	2m 57s
Build and test software	14m 59s
Earl Grey for CW310 / Build bitstream	1m 49s
Earl Grey for CW310 Hyperdebug / Build bitstream	1m 42s
Earl Grey for CW340 / Build bitstream	1m 47s
CW310 Test ROM Tests / FPGA test	3m 48s
CW310 ROM Tests / FPGA test	48m 29s
CW310 ROM_EXT Tests / FPGA test	5m 49s
CW340 Test ROM Tests / FPGA test	10m 49s
CW340 ROM_EXT Tests / FPGA test	6m 40s
CW340 ROM Tests / FPGA test	2m 43s
CW340 Manufacturing Tests / FPGA test	9m 0s
CW340 SiVal Tests / FPGA test	15m 11s
CW340 SiVal ROM_EXT Tests / FPGA test	4m 24s
Cache bitstreams to GCP	3m 31s
CW310 SiVal ROM_EXT Tests / FPGA test	23m 49s
CW310 SiVal Tests / FPGA test	21m 24s
CW310 Manufacturing Tests / FPGA test	25m 20s
Verify FPGA jobs	52s
	5h 26m 3s

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