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[multitop_dev] Reinstate all_files and remove files from opentitan_{ip,top} #2353

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[multitop_dev] Reinstate all_files and remove files from opentitan_{ip,top}

[multitop_dev] Reinstate all_files and remove files from opentitan_{ip,top} #2353

Triggered via pull request November 25, 2024 13:35
@pamaurypamaury
opened #25375
pamaury:multitop_dev_all_files
Status Cancelled
Total duration 13m 16s
Artifacts 2

ci.yml

on: pull_request
Lint (quick)
2m 52s
Lint (quick)
Earl Grey for CW340  /  Build bitstream
2m 13s
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
2m 19s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW310  /  Build bitstream
2m 9s
Earl Grey for CW310 / Build bitstream
Lint (slow)
10m 6s
Lint (slow)
Airgapped build
6m 1s
Airgapped build
Verible lint
1m 13s
Verible lint
Verilated English Breakfast
6m 48s
Verilated English Breakfast
CW305's Bitstream
1m 31s
CW305's Bitstream
Build Docker Containers
2m 44s
Build Docker Containers
Build and test software
2m 1s
Build and test software
CW340 Manufacturing Tests  /  FPGA test
CW340 Manufacturing Tests / FPGA test
CW340 ROM Tests  /  FPGA test
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
CW340 SiVal Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
CW340 Test ROM Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
CW310 Manufacturing Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
CW310 SiVal Tests / FPGA test
CW310 ROM Tests  /  FPGA test
CW310 ROM Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
CW310 ROM_EXT Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
CW310 Test ROM Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
26s
Verify FPGA jobs
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Annotations

15 errors and 3 warnings
CW305's Bitstream
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.
Earl Grey for CW310 / Build bitstream
Process completed with exit code 1.
Airgapped build
Process completed with exit code 2.
Verilated English Breakfast
Process completed with exit code 1.
Earl Grey for CW310 Hyperdebug / Build bitstream
Process completed with exit code 1.
Earl Grey for CW340 / Build bitstream
Process completed with exit code 1.
Verify FPGA jobs
Canceling since a higher priority waiting request for 'CI-refs/pull/25375/merge' exists
Verify FPGA jobs
The operation was canceled.
Verify FPGA jobs
Process completed with exit code 1.
Lint (slow)
Canceling since a higher priority waiting request for 'CI-refs/pull/25375/merge' exists
Lint (slow)
The operation was canceled.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Earl Grey for CW310 / Build bitstream
No files were found with the provided path: build-out. No artifacts will be uploaded.
Earl Grey for CW310 Hyperdebug / Build bitstream
No files were found with the provided path: build-out. No artifacts will be uploaded.
Earl Grey for CW340 / Build bitstream
No files were found with the provided path: build-out. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
sw_build_test-test-results
200 Bytes
verilated_englishbreakfast
6.48 MB