Add direct control of tempsens core for debug

src/tempsens.v

@@ -30,6 +30,7 @@ module tempsens (
 	input wire 					clk,
 	input wire [N_VDAC-1:0] 	i_dac_code,
 	input wire [3:0] 			i_dbg_sel,
+	input wire [1:0]			i_dbg_ts,
 	// main outputs
 	output wire [N_TEMP-1:0]	o_res,
 	output wire [3:0] 			o_dbg
@@ -50,6 +51,7 @@ module tempsens (
 		.clk(clk),
 		.i_dac_code(i_dac_code),
 		.i_dbg_sel(i_dbg_sel),
+		.i_dbg_ts(i_dbg_ts),
 		.o_res(o_res),
 		.o_dbg(o_dbg),
 		.i_ts_tempdelay(ts_tempdelay),

src/tempsens_core.v

@@ -29,8 +29,10 @@
 `define __TEMPSENS_CORE__
 
 `default_nettype none
+`ifdef SIM
 `timescale 1ns/1ns
-`ifndef SIMULATION
+`endif
+`ifndef SIM
 `include "tempsens_vdac.v"
 `endif
 //`include "/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
@@ -41,7 +43,7 @@ module tempsens_core #( parameter DAC_RESOLUTION=6, parameter CAP_LOAD=16 )(
       input wire [DAC_RESOLUTION-1:0]     i_dac_data,
       input wire                          i_dac_en,
       input wire                          i_precharge_n,
-`ifdef SIMULATION
+`ifdef SIM
       output reg                          o_tempdelay
 `else
       output wire                         o_tempdelay
@@ -51,7 +53,7 @@ module tempsens_core #( parameter DAC_RESOLUTION=6, parameter CAP_LOAD=16 )(
       // during precharging and measurement, o_tempdelay stays high
       // a 1->0 transition marks the end of the measurement time
 
-`ifdef SIMULATION
+`ifdef SIM
       wire dac0, dac1, dac_change;
       assign dac0 = ~|i_dac_data;
       assign dac1 = &i_dac_data;

src/tempsens_ctrl.v

@@ -23,6 +23,7 @@ module tempsens_ctrl #( parameter N_TEMP=20, N_VDAC=6 )(
 	input wire clk,
 	input wire [N_VDAC-1:0] i_dac_code,
 	input wire [3:0] i_dbg_sel,
+	input wire [1:0] i_dbg_ts,
 	// main outputs
 	output wire [N_TEMP-1:0] o_res,
 	output wire [3:0] o_dbg,
@@ -87,22 +88,27 @@ module tempsens_ctrl #( parameter N_TEMP=20, N_VDAC=6 )(
 	wire in_transition = in_transition_ph1 || in_transition_ph2;
 	wire in_measurement = (state == ST_MEASURE);
 	wire is_done = (state == ST_DONE);
+	wire in_debug = (i_dbg_sel == 4'd15);
 
 	// signals going in and out of temperature-dependent delay line
     wire tempsens_en, tempsens_measure;
 	wire [N_VDAC-1:0] tempsens_dat;
 
-	// create temperature sensor input signal based on state signals, gate output to
-	assign tempsens_en = (in_precharge || in_transition || in_measurement) ? 1'b1 : 1'b0;
-	assign tempsens_dat =		in_precharge		? VMAX :
+	// create temperature sensor input signal based on state signals
+	// debug mode 15 allows direct control of tempsensor core from outside
+	assign tempsens_en = 		in_debug ? i_dbg_ts[0] :
+								(in_precharge || in_transition || in_measurement) ? 1'b1 : 1'b0;
+
+	assign tempsens_dat =		in_debug 			? i_dac_code :
+								in_precharge		? VMAX :
 								in_transition		? VMIN :
-								in_measurement		? i_dac_code :
-								VMAX;
-	assign tempsens_measure = 	in_precharge		? 1'b0 :
+								in_measurement		? i_dac_code : VMAX;
+
+	assign tempsens_measure =	in_debug 			? i_dbg_ts[1] :
+								in_precharge		? 1'b0 :
 								in_transition_ph1	? 1'b0 :
 								in_transition_ph2	? 1'b1 :
-								in_measurement 		? 1'b1 :
-								1'b0;
+								in_measurement 		? 1'b1 : 1'b0;
 
 
 	// debug vectors
@@ -123,8 +129,7 @@ module tempsens_ctrl #( parameter N_TEMP=20, N_VDAC=6 )(
 			4'd12: dbg = tempsens_final[11:08];
 			4'd13: dbg = tempsens_final[15:12];
 			4'd14: dbg = tempsens_final[19:16];
-			default:
-				  dbg = 4'b1010;
+			4'd15: dbg = {1'b0,o_ts_en,o_ts_prechrgn,i_ts_tempdelay};
 		endcase
 	end
 

src/tempsens_vdac_cell.v

@@ -27,8 +27,14 @@
 `define __TEMPSENS_VDAC_CELL__
 
 `default_nettype none
+/* verilator lint_off INCABSPATH */
+/* verilator lint_off UNUSEDSIGNAL */
+/* verilator lint_off DECLFILENAME */
 //`include "/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
 //`include "/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+/* verilator lint_on INCABSPATH */
+/* verilator lint_on UNUSEDSIGNAL */
+/* verilator lint_on DECLFILENAME */
 
 module tempsens_vdac_cell #(parameter PARALLEL_CELLS = 4) (
 	input wire	i_sign,

src/tt_um_hpretl_tt06_tempsens.v

@@ -56,6 +56,7 @@ module tt_um_hpretl_tt06_tempsens (
 		.clk(clk),
 		.i_dac_code(dac_code),
     .i_dbg_sel(uio_in[3:0]),
+    .i_dbg_ts(out_sel),
 		.o_res(out_wide),
 		.o_dbg(uio_out[7:4])
 	);