Try to fix build fails

src/config.tcl

@@ -31,6 +31,7 @@ set ::env(LINTER_INCLUDE_PDK_MODELS) 1
 # Avoid messing around with analog signals
 set ::env(RSZ_DONT_TOUCH_RX) "_ana_"
 set ::env(QUIT_ON_SYNTH_CHECKS) 0
+set ::env(QUIT_ON_SETUP_VIOLATIONS) 0
 
 # !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
 # !!! DO NOT CHANGE ANYTHING BELOW THIS POINT !!!

test/Makefile

@@ -5,14 +5,15 @@
 SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 SRC_DIR = $(PWD)/../src
-PROJECT_SOURCES = project.v
+PROJECT_SOURCES = tt_um_hpretl_tt06_tempsens.v
 
 ifneq ($(GATES),yes)
 
 # RTL simulation:
 SIM_BUILD				= sim_build/rtl
 VERILOG_SOURCES += $(addprefix $(SRC_DIR)/,$(PROJECT_SOURCES))
 COMPILE_ARGS 		+= -I$(SRC_DIR)
+COMPILE_ARGS		+= -DSIMULATION
 
 else
 
@@ -22,6 +23,7 @@ COMPILE_ARGS    += -DGL_TEST
 COMPILE_ARGS    += -DFUNCTIONAL
 COMPILE_ARGS    += -DUSE_POWER_PINS
 COMPILE_ARGS    += -DSIM
+COMPILE_ARGS	+= -DSIMULATION
 COMPILE_ARGS    += -DUNIT_DELAY=\#1
 VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
 VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v

test/tb.v

@@ -3,6 +3,7 @@
 /* This testbench just instantiates the module and makes some convenient wires
    that can be driven / tested by the cocotb test.py.
 */
+
 module tb ();
 
   // Dump the signals to a VCD file. You can view it with gtkwave.