add some more store tests

hazel-sudz · Jan 11, 2024 · 8f2076e · 8f2076e
1 parent e7075df
commit 8f2076e
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Showing 4 changed files with 105 additions and 17 deletions.
diff --git a/src/asm/out/storeload_2.memh b/src/asm/out/storeload_2.memh
@@ -0,0 +1,8 @@
+0ff00093 // PC=0x0 line=1: addi  x1, x0, 255              # x01 = 255 (32'b00000000000000000000000011111111)
+40000113 // PC=0x4 line=2: addi  x2, x0, 1024             # x02 = 1024
+00112023 // PC=0x8 line=3: sw  x1, 0(x2)                  # (MEM:1024) = 255 (32'b00000000000000000000000011111111)
+00010183 // PC=0xc line=4: lb  x3, 0(x2)                  # x03 = -1 (32'b11111111111111111111111111111111)
+00011203 // PC=0x10 line=5: lh  x4, 0(x2)                  # x04 = 255 (32'b00000000000000000000000011111111)
+00012283 // PC=0x14 line=6: lw  x5, 0(x2)                  # x05 = 255 (32'b00000000000000000000000011111111)
+00014303 // PC=0x18 line=7: lbu x6, 0(x2)                  # x06 = 255 (32'b00000000000000000000000011111111)
+00015383 // PC=0x1c line=8: lhu x7, 0(x2)                  # x07 = 255 (32'b00000000000000000000000011111111)
diff --git a/src/asm/lb.s → src/asm/storeload_2.s b/src/asm/lb.s → src/asm/storeload_2.s
@@ -1,19 +1,24 @@
-addi  x1, x0, 1040             # x01 = 1040 (16 + 1024)
+addi  x1, x0, 255              # x01 = 255 (32'b00000000000000000000000011111111)
 addi  x2, x0, 1024             # x02 = 1024 
-sb  x1, 0(x2)                  # (MEM:1024) = 16
-lb  x3, 0(x2)                  # x03 = 16
+sw  x1, 0(x2)                  # (MEM:1024) = 255 (32'b00000000000000000000000011111111)
+lb  x3, 0(x2)                  # x03 = -1 (32'b11111111111111111111111111111111)
+lh  x4, 0(x2)                  # x04 = 255 (32'b00000000000000000000000011111111)
+lw  x5, 0(x2)                  # x05 = 255 (32'b00000000000000000000000011111111)
+lbu x6, 0(x2)                  # x06 = 255 (32'b00000000000000000000000011111111)
+lhu x7, 0(x2)                  # x07 = 255 (32'b00000000000000000000000011111111)
+
 
 #TESTASSERTOUTPUT|---------------------------------------|
 #TESTASSERTOUTPUT| Register File State :)                |
 #TESTASSERTOUTPUT|---------------------------------------|
 #TESTASSERTOUTPUT|    x00, zero = 0x00000000 (         0)|
-#TESTASSERTOUTPUT|      x01, ra = 0x00000410 (      1040)|
+#TESTASSERTOUTPUT|      x01, ra = 0x000000ff (       255)|
 #TESTASSERTOUTPUT|      x02, sp = 0x00000400 (      1024)|
-#TESTASSERTOUTPUT|      x03, gp = 0x00000010 (        16)|
-#TESTASSERTOUTPUT|      x04, tp = 0x00000000 (         0)|
-#TESTASSERTOUTPUT|      x05, t0 = 0x00000000 (         0)|
-#TESTASSERTOUTPUT|      x06, t1 = 0x00000000 (         0)|
-#TESTASSERTOUTPUT|      x07, t2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x03, gp = 0xffffffff (        -1)|
+#TESTASSERTOUTPUT|      x04, tp = 0x000000ff (       255)|
+#TESTASSERTOUTPUT|      x05, t0 = 0x000000ff (       255)|
+#TESTASSERTOUTPUT|      x06, t1 = 0x000000ff (       255)|
+#TESTASSERTOUTPUT|      x07, t2 = 0x000000ff (       255)|
 #TESTASSERTOUTPUT|      x08, s0 = 0x00000000 (         0)|
 #TESTASSERTOUTPUT|      x09, s1 = 0x00000000 (         0)|
 #TESTASSERTOUTPUT|      x10, a0 = 0x00000000 (         0)|
@@ -38,4 +43,4 @@ lb  x3, 0(x2)                  # x03 = 16
 #TESTASSERTOUTPUT|      x29, t4 = 0x00000000 (         0)|
 #TESTASSERTOUTPUT|      x30, t5 = 0x00000000 (         0)|
 #TESTASSERTOUTPUT|      x31, t6 = 0x00000000 (         0)|
-#TESTASSERTOUTPUT|---------------------------------------|
+#TESTASSERTOUTPUT|---------------------------------------|
diff --git a/src/asm/test/storeload_2.result b/src/asm/test/storeload_2.result
@@ -0,0 +1,50 @@
+Usage:
+ ./rv32_simulator +initial_memory=path/to/memh/file
+  Additional arguments:
+    +initial_memory=path/to/memh/file
+        Required: path to a memh file that containes the assembled binary to run.
+    +max_cycles=NUMBER_OF_CYCLES_TO_RUN
+    +wave_fn=path/to/wave/file
+        default is rv32_simulator.fst
+    +final_memory=path/to/memh/file
+        If provided, the final memory contents will be saved here. Use this to debug your store instructions.
+WARNING: ./tests/provided/bytewise_distributed_ram.sv:58: $readmemh(../asm/out/storeload_2.memh): Not enough words in the file for the requested range [0:1023].
+Running simulation of memory ../asm/out/storeload_2.memh for up to       10000 cycles. Waves will be stored to rv32_simulator.fst.
+FST info: dumpfile rv32_simulator.fst opened for output.
+Ran       10000 cycles, finishing.
+#TESTASSERTOUTPUT|---------------------------------------|
+#TESTASSERTOUTPUT| Register File State :)                |
+#TESTASSERTOUTPUT|---------------------------------------|
+#TESTASSERTOUTPUT|    x00, zero = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x01, ra = 0x000000ff (       255)|
+#TESTASSERTOUTPUT|      x02, sp = 0x00000400 (      1024)|
+#TESTASSERTOUTPUT|      x03, gp = 0xffffffff (        -1)|
+#TESTASSERTOUTPUT|      x04, tp = 0x000000ff (       255)|
+#TESTASSERTOUTPUT|      x05, t0 = 0x000000ff (       255)|
+#TESTASSERTOUTPUT|      x06, t1 = 0x000000ff (       255)|
+#TESTASSERTOUTPUT|      x07, t2 = 0x000000ff (       255)|
+#TESTASSERTOUTPUT|      x08, s0 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x09, s1 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x10, a0 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x11, a1 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x12, a2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x13, a3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x14, a4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x15, a5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x16, a6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x17, a7 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x18, s2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x19, s3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x20, s4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x21, s5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x22, s6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x23, s7 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x24, s8 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x25, s9 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|     x26, s10 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|     x27, s11 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x28, t3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x29, t4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x30, t5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x31, t6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|---------------------------------------|
diff --git a/src/components/src/cpu/rv32i_multicycle_core.sv b/src/components/src/cpu/rv32i_multicycle_core.sv
@@ -98,12 +98,19 @@ module rv32i_multicycle_core(
     wire zero;
     wire equal;
 
-
-   /* ---------------------- Non-Architectural Register Signals ---------------------- */
     logic alu_last_ena;
     wire [31:0] alu_last; // Not a descriptive name, but this is what it's called in the text.
+
+
+   /* ---------------------- Non-Architectural Register Signals ---------------------- */
+
+
+    /* -------------------------------------------------------------------------------------------------------------------*/
+    /*                                              Memory Decoder (begin)                                                */
+    /* -------------------------------------------------------------------------------------------------------------------*/
+    logic [31:0] mem_data, mem_data_extended;
     logic mem_data_ena;
-    wire [31:0] mem_data;
+
     enum logic [2:0] {MEM_SRC_PC, MEM_SRC_ALU_LAST, MEM_SRC_RESULT} mem_src;
 
     always_comb begin : mem_src_signals
@@ -112,21 +119,38 @@ module rv32i_multicycle_core(
             MEM_SRC_ALU_LAST: mem_addr = alu_last;
         endcase
     end
+
+    always_comb begin: mem_extended_decoder
+        case(funct3)
+            3'b000: mem_data_extended = {{24{mem_data[7]}}, mem_data[7:0]};         // load byte, sign extend 7:0
+            3'b001: mem_data_extended = {{16{mem_data[15]}}, mem_data[15:0]};       // load byte, sign extend 15:0
+            3'b010: mem_data_extended = mem_data;                                   // load word, 31:0
+            3'b100: mem_data_extended = mem_data;                                   // load byte unsigned, 7:0 (memory already masks read for us)
+            3'b101: mem_data_extended = mem_data;                                   // load half unsigned, 15:0 (memory already masks read for us)
+        endcase 
+    end
+
+    register #(.N(32), .RESET_VALUE(32'b0)) MEM_DATA_REGISTER (
+    .clk(clk), .rst(rst), .ena(mem_data_ena), .d(mem_rd_data), .q(mem_data)
+    );
+
+    /* -------------------------------------------------------------------------------------------------------------------*/
+    /*                                              Memory Decoder (end)                                                  */
+    /* -------------------------------------------------------------------------------------------------------------------*/
 
 
     register #(.N(32), .RESET_VALUE(32'b0)) ALU_RESULT_REGISTER (
     .clk(clk), .rst(rst), .ena(alu_last_ena), .d(alu_result), .q(alu_last)
     );
 
-    register #(.N(32), .RESET_VALUE(32'b0)) MEM_DATA_REGISTER (
-    .clk(clk), .rst(rst), .ena(mem_data_ena), .d(mem_rd_data), .q(mem_data)
-    );
+
 
 
     /* ---------------------- Result SRC Signals ---------------------- */
     enum logic [2:0] {
         RESULT_SRC_ALU, 
         RESULT_SRC_MEM_DATA, 
+        RESULT_SRC_MEM_DATA_EXTENDED,
         RESULT_SRC_ALU_LAST, 
         RESULT_SRC_PC_NEXT_INSTRUCTION,
         RESULT_SRC_IMMEDIATE
@@ -137,6 +161,7 @@ module rv32i_multicycle_core(
         case(result_src)
             RESULT_SRC_ALU: result = alu_result;
             RESULT_SRC_MEM_DATA: result = mem_data;
+            RESULT_SRC_MEM_DATA_EXTENDED: result = mem_data_extended;
             RESULT_SRC_ALU_LAST: result = alu_last;
             RESULT_SRC_PC_NEXT_INSTRUCTION: result = PC_next_instruction;
             RESULT_SRC_IMMEDIATE: result = extended_immediate;
@@ -286,7 +311,7 @@ module rv32i_multicycle_core(
             // LOAD INSTRUCTION write back to RF 
             S_MEMWB: begin
                 set_default;
-                result_src = RESULT_SRC_MEM_DATA;
+                result_src = RESULT_SRC_MEM_DATA_EXTENDED;
                 reg_write = 1;
                 pc_next_src = PC_NEXT_INSTRUCTION;
                 PC_ena = 1;