add a jalr state

src/asm/jal.s

@@ -0,0 +1,10 @@
+jal x1, jump      # x01 = 4
+
+addi x1, x1, 10   # x1 += 10
+beq x0, x0, trap  # halt
+
+jump:
+jalr x1, x1, 0    # x1 = 20, jump to addi 
+
+trap: 
+

src/asm/out/jal.memh

@@ -0,0 +1,4 @@
+00c000ef // PC=0x0 line=1: jal x1, jump      # x01 = 4
+00a08093 // PC=0x4 line=3: addi x1, x1, 10   # x1 += 10
+00000463 // PC=0x8 line=4: beq x0, x0, trap  # halt
+000080e7 // PC=0xc line=7: jalr x1, x1, 0    # x1 = 20, jump to addi

src/asm/test/jal.result

@@ -0,0 +1,50 @@
+Usage:
+ ./rv32_simulator +initial_memory=path/to/memh/file
+  Additional arguments:
+    +initial_memory=path/to/memh/file
+        Required: path to a memh file that containes the assembled binary to run.
+    +max_cycles=NUMBER_OF_CYCLES_TO_RUN
+    +wave_fn=path/to/wave/file
+        default is rv32_simulator.fst
+    +final_memory=path/to/memh/file
+        If provided, the final memory contents will be saved here. Use this to debug your store instructions.
+WARNING: ./tests/provided/bytewise_distributed_ram.sv:58: $readmemh(../asm/out/jal.memh): Not enough words in the file for the requested range [0:1023].
+Running simulation of memory ../asm/out/jal.memh for up to       10000 cycles. Waves will be stored to rv32_simulator.fst.
+FST info: dumpfile rv32_simulator.fst opened for output.
+Ran       10000 cycles, finishing.
+#TESTASSERTOUTPUT|---------------------------------------|
+#TESTASSERTOUTPUT| Register File State :)                |
+#TESTASSERTOUTPUT|---------------------------------------|
+#TESTASSERTOUTPUT|    x00, zero = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x01, ra = 0x00000010 (        16)|
+#TESTASSERTOUTPUT|      x02, sp = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x03, gp = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x04, tp = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x05, t0 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x06, t1 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x07, t2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x08, s0 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x09, s1 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x10, a0 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x11, a1 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x12, a2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x13, a3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x14, a4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x15, a5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x16, a6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x17, a7 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x18, s2 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x19, s3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x20, s4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x21, s5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x22, s6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x23, s7 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x24, s8 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x25, s9 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|     x26, s10 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|     x27, s11 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x28, t3 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x29, t4 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x30, t5 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|      x31, t6 = 0x00000000 (         0)|
+#TESTASSERTOUTPUT|---------------------------------------|

src/components/src/cpu/rv32i_multicycle_core.sv

@@ -35,7 +35,7 @@ module rv32i_multicycle_core(
         S_ALUWB = 6, 
         S_MEMWRITE = 7,
         S_BRANCH = 8,
-        S_JAL = 9
+        S_JALR = 9
     } state;
 
     /* ---------------------- Standard Control Signals ---------------------- */
@@ -395,17 +395,32 @@ module rv32i_multicycle_core(
                             alu_src_a = ALU_SRC_A_OLD_PC;
                             alu_src_b = ALU_SRC_B_IMM;
                         end
-                        `OP_JALR: begin
-                            alu_src_a = ALU_SRC_A_RF;
-                            alu_src_b = ALU_SRC_B_IMM;
-                        end
                     endcase
                 end
         endcase
     end
     /* -------------------------------------------------------------------------------------------------------------------*/
     /*                                              DATAPATH for decode / branch target (end)                             */
     /* -------------------------------------------------------------------------------------------------------------------*/
+
+    /* -------------------------------------------------------------------------------------------------------------------*/
+    /*                                              DATAPATH for JALR (start)                                             */
+    /* -------------------------------------------------------------------------------------------------------------------*/
+    always_comb begin: datapath_jalr
+        case(state)
+            // for jalr we need one more cycle to go to the register file compared to jal which can just straight jump
+            S_JALR: begin
+                set_default;
+                alu_control = ALU_ADD;
+                alu_last_ena = 1;
+                alu_src_a = ALU_SRC_A_RF;
+                alu_src_b = ALU_SRC_B_IMM;
+            end
+        endcase
+    end
+    /* -------------------------------------------------------------------------------------------------------------------*/
+    /*                                              DATAPATH for JALR (end)                                               */
+    /* -------------------------------------------------------------------------------------------------------------------*/
 
     /* -------------------------------------------------------------------------------------------------------------------*/
     /*                                              DATAPATH for branch (begin)                                           */
@@ -481,10 +496,11 @@ module rv32i_multicycle_core(
                         `OP_R_EXECUTE: state <= S_EXECUTE_RI;
                         `OP_BRANCH: state <= S_BRANCH;
                         `OP_JAL: state <= S_ALUWB;
-                        `OP_JALR: state <= S_ALUWB;
+                        `OP_JALR: state <= S_JALR;
                     endcase
                 end
                 S_EXECUTE_RI: state <= S_ALUWB;
+                S_JALR : state <= S_ALUWB;
                 S_ALUWB: state <= S_FETCH;
                 S_MEMADR: begin
                     case(op)