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LICENSE
LICENSE
 
 
README.md
README.md
 
 
add.vhd
add.vhd
 
 
alu.vhd
alu.vhd
 
 
alu_control.vhd
alu_control.vhd
 
 
compare.vhd
compare.vhd
 
 
control_unit.vhd
control_unit.vhd
 
 
control_unit.vhd.bak
control_unit.vhd.bak
 
 
data_memory.vhd
data_memory.vhd
 
 
hazard_unit.vhd
hazard_unit.vhd
 
 
hazard_unit.vhd.bak
hazard_unit.vhd.bak
 
 
hungdeptrai.cr.mti
hungdeptrai.cr.mti
 
 
hungdeptrai.mpf
hungdeptrai.mpf
 
 
instruction_memory.vhd
instruction_memory.vhd
 
 
instruction_memory.vhd.bak
instruction_memory.vhd.bak
 
 
mips_pipeline.vhd
mips_pipeline.vhd
 
 
mips_pipeline.vhd.bak
mips_pipeline.vhd.bak
 
 
mux2_1.vhd
mux2_1.vhd
 
 
mux2_1_logic.vhd
mux2_1_logic.vhd
 
 
mux4_1.vhd
mux4_1.vhd
 
 
pc.vhd
pc.vhd
 
 
pc.vhd.bak
pc.vhd.bak
 
 
pipeline.asm.rpt
pipeline.asm.rpt
 
 
pipeline.cr.mti
pipeline.cr.mti
 
 
pipeline.done
pipeline.done
 
 
pipeline.fit.rpt
pipeline.fit.rpt
 
 
pipeline.fit.summary
pipeline.fit.summary
 
 
pipeline.flow.rpt
pipeline.flow.rpt
 
 
pipeline.map.rpt
pipeline.map.rpt
 
 
pipeline.map.summary
pipeline.map.summary
 
 
pipeline.mpf
pipeline.mpf
 
 
pipeline.pin
pipeline.pin
 
 
pipeline.pof
pipeline.pof
 
 
pipeline.qpf
pipeline.qpf
 
 
pipeline.qsf
pipeline.qsf
 
 
pipeline.qws
pipeline.qws
 
 
pipeline.sof
pipeline.sof
 
 
pipeline.tan.rpt
pipeline.tan.rpt
 
 
pipeline_description.txt
pipeline_description.txt
 
 
plus4.vhd
plus4.vhd
 
 
plus8.vhd
plus8.vhd
 
 
plus8.vhd.bak
plus8.vhd.bak
 
 
regD.vhd
regD.vhd
 
 
regD.vhd.bak
regD.vhd.bak
 
 
regE.vhd
regE.vhd
 
 
regE.vhd.bak
regE.vhd.bak
 
 
regM.vhd
regM.vhd
 
 
regW.vhd
regW.vhd
 
 
register_file.vhd
register_file.vhd
 
 
register_file.vhd.bak
register_file.vhd.bak
 
 
shft_left.vhd
shft_left.vhd
 
 
shft_left_s.vhd
shft_left_s.vhd
 
 
sign_zero_extend.vhd
sign_zero_extend.vhd
 
 
vsim.wlf
vsim.wlf
 
 
work.cr.mti
work.cr.mti
 
 
work.mpf
work.mpf
 
 
zero_extend.vhd
zero_extend.vhd
 
 

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Mips-Pipelined

Me and Hung created a pipelined MIPS working from detailed mapping and selected commands.

Image of The block diagram

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A pipelined mips PU in VHDL fully running

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