pipeline.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 132 02/25/2009 SJ Web Edition
# Date created = 23:09:22  November 29, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		pipeline_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F672C7
set_global_assignment -name TOP_LEVEL_ENTITY mips_pipeline
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:09:22  NOVEMBER 29, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION 9.0
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -entity pipeline -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -entity pipeline -section_id "Root Region"
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name VHDL_FILE add.vhd
set_global_assignment -name VHDL_FILE alu.vhd
set_global_assignment -name VHDL_FILE alu_control.vhd
set_global_assignment -name VHDL_FILE compare.vhd
set_global_assignment -name VHDL_FILE control_unit.vhd
set_global_assignment -name VHDL_FILE data_memory.vhd
set_global_assignment -name VHDL_FILE hazard_unit.vhd
set_global_assignment -name VHDL_FILE instruction_memory.vhd
set_global_assignment -name VHDL_FILE mips_pipeline.vhd
set_global_assignment -name VHDL_FILE mux2_1.vhd
set_global_assignment -name VHDL_FILE mux4_1.vhd
set_global_assignment -name VHDL_FILE pc.vhd
set_global_assignment -name VHDL_FILE plus4.vhd
set_global_assignment -name VHDL_FILE plus8.vhd
set_global_assignment -name VHDL_FILE regD.vhd
set_global_assignment -name VHDL_FILE regE.vhd
set_global_assignment -name VHDL_FILE regM.vhd
set_global_assignment -name VHDL_FILE regW.vhd
set_global_assignment -name VHDL_FILE register_file.vhd
set_global_assignment -name VHDL_FILE shft_left.vhd
set_global_assignment -name VHDL_FILE shft_left_s.vhd
set_global_assignment -name VHDL_FILE sign_zero_extend.vhd
set_global_assignment -name VHDL_FILE zero_extend.vhd
set_global_assignment -name VHDL_FILE mux2_1_logic.vhd