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PIODev Board Memory Mapping

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Nicolas "Pixel" Noble edited this page Jun 29, 2020 · 3 revisions

Preparation

In order to fully unlock the PIODev Board's capabilities, one needs to run the following code first:

*((volatile uint32_t *) 0x1f801008) = (23 << 16) | 0x2422;

This will do two things: enlarge the bus width to utilize the full 8MB memory map available, and speed up both reads and writes to the bus.

Current caveats

The current verilog code will forcibly try to utilize the !CS2 line, meaning that if you do not have the Switch Board installed to hook into this signal, lots of bad things will happen. Enhancement of the verilog code should happen in the future to allow for the hardware configuration dip switches to indicate if !CS2 needs an override or not.

Memory mapping

The current verilog code for the PIO Dev board is crude, and creates the following hardcoded memory mapping:

  • 0x1f000000 - 0x1f1fffff: soldered flash
  • 0x1f200000 - 0x1f3fffff: socketed flash - also mirrored on 0xbfc00000 through the !CS2 override.
  • 0x1f400000 - 0x1f5fffff: sram
  • 0x1f600000: FT2232H's port A data register; see the FT2232H's datasheet for more information
  • 0x1f600001: FT2232H's port A control register; see the FT2232H's datasheet for more information
  • 0x1f600002: FT2232H's port B data register; see the FT2232H's datasheet for more information
  • 0x1f600003: FT2232H's port B control register; see the FT2232H's datasheet for more information
  • 0x1f600004: CH375B's data register; see the CH375B's datasheet for more information
  • 0x1f600005: CH375B's control register; see the CH375B's datasheet for more information
  • 0x1f600006: LEDs and dip switches. A read will return the inverted value of the switches that are toggled on or off. A write will light up the corresponding LEDs.
  • 0x1f600007: configuration bits. Currently unused, and acts as an 8-bits register.

Future work

More flexible memory mapping

The most essential feature for this board is to be able to swap the ROM chips for the SRAM. This would mean something along these lines:

memcpy(BIOSBaseAddress, PIODevBoardSRAM, 512 * 1024);
*PIODevBoardConfigurationBits |= PIODevBoardConfiguration_MAP_SRAM_TO_BIOS;

This will require more flexibility in the various booleans that the verilog currently has to activate the various chips and their two pages.

GameShark / Pro Action Replay emulation

Since the CPLD has the same sort of address lines hooked to it as the PLA from the GameShark or the PAR carts, it should be possible to emulate in verilog the behavior of these devices with regards to the dip switch, and the communication port, redirecting the former to one of the 10 dip switches on board, and the latter to one of the ports of the FT2232H.

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