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DTL H2000 list of chips
Download datasheet - Online datasheet
Note that the datasheet is about the H variant of the chip, which has a Bus Hold mechanism. This isn't the case on the original chip. See the LVT-to-LVTH Conversion document for more details.
Its feature seems to be gating the address bus for the 68-pins PIO plug. The other devices that need access to the address bus seem to do so directly through the 100-pins bridge connector.
Download datasheet - Online datasheet
This little PLD of 600 gates and 36 user pins is for now unknown in function, although it's possible to make educated guesses, as it's being connected to a lot of output enable and address lines. The name on the sticker "ADD 1" might indicate its function as an address demuxer, which typically doesn't hold any sort of state. Ideally, a dump of its EEPROM should be performed, in order to full reverse engineer what it does, but listing all of its inputs and outputs might be enough to build a LUT of what it currently does. If the security bit is enabled, it might not be possible to dump the EEPROM without decapping and destroying it, although finding blank replacement parts is easy. The company break-ic claims to be able to reverse it.
One odd particularity as of now is that the chip is sitting in between address lines A7 and A18, at least for the U731 ROM chip. More investigation is needed. The reason for needing to intercept these two address lines is currently unknown.
Download datasheet - Online datasheet
Note that the datasheet is about the H variant of the chip, which has a Bus Hold mechanism. This isn't the case on the original chip. See the LVT-to-LVTH Conversion document for more details.
This chip is responsible for gating the data bus of the 68-pins PIO port. It is connected to the U732 chip on the bridge connector side.
Download datasheet - Online datasheet
Note that the datasheet is about the H variant of the chip, which has a Bus Hold mechanism. This isn't the case on the original chip. See the LVT-to-LVTH Conversion document for more details.
This chip is used to buffer address lines A0 to A7, and various control lines for the PIO port.
Download datasheet - Online datasheet
Note that the datasheet is about the H variant of the chip, which has a Bus Hold mechanism. This isn't the case on the original chip. See the LVT-to-LVTH Conversion document for more details.
This chip is used to buffer address lines A8 to A23 for the PIO port.
Download datasheet - Online datasheet
This bigger PLD of 3200 gates and 64 user pins is for now unknown in function, although it's possible to make educated guesses, as it's being connected to a lot of data lines. Its label "CNTL 1" might indicate it's a controller of sorts. This could prove harder to guess its role than the U43 PLD, as it most likely has internal states. Ideally, a dump of its EEPROM should be performed, in order to full reverse engineer what it does. If the security bit is enabled, it might not be possible to dump the EEPROM without decapping and destroying it, although finding blank replacement parts is easy. The company break-ic claims to be able to reverse it.
Download datasheet - Online datasheet
This is the ROM that boots the main MIPS CPU. Lines D0 to D14 are connected to U732. D15/A-1 is connected directly to the 100 pins bridge connector, on A0. Note that the datasheet has address lines from A17 to A-1, due to the way the chip can switch between 8 bits and 16 bits mode. The DTL-H2000 however only uses it in 8 bits mode, hence the reason pin 29 is connected to A0, and that all the address line numbers are shifted by one. The rest of this document will refer to the address lines+1, for clarity.
One peculiar feature is that data lines D8-D14 needed not to be connected, but they are routed anyway.
The chip is powered using 3.3v, and so all of its IO uses this voltage.
Almost all of its 19 address lines are connected to the 100 pins bridge connector, except for pins 1 and 3, A18 and A7, which are connected to U43 instead.
Given the general behaviour and speed, it would be extremely simple to replace this chip by a flash, given a small adapter PCB. The goal would be to easily reprogram the ROM to run different diagnostics or tests.
This is the ROM that boots the main MIPS CPU.
Download datasheet - Online datasheet
Note that the datasheet is about the H variant of the chip, which has a Bus Hold mechanism. This isn't the case on the original chip. See the LVT-to-LVTH Conversion document for more details.
This chip is responsible for gating the data bus of the following components on the PIO board:
- The U731 ROM.
- Note that 15 out of the 16 data lines are connected to the bios, and IO15/A-1 of the bios is used as an address line, as !BYTE is always asserted low, which feels like a waste of routing.
- The U730 PLD.
- Only the first 8 bits are connected.
- The CD-ROM controller.
- Only the first 8 bits are connected.
- The ISA FIFOs.
It is connected to the U64 chip on its bridge connector side.
Download datasheet - Online datasheet
Download datasheet - Online datasheet
Note that the datasheet is about the H variant of the chip, which has a Bus Hold mechanism. This isn't the case on the original chip. See the LVT-to-LVTH Conversion document for more details.