Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add cm config #303

Merged
merged 27 commits into from
Jan 1, 2025
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
27 commits
Select commit Hold shift + click to select a range
1e00195
Add cm config
kgugala Dec 27, 2024
54ab41b
waive rst_vec and nmi_vec signals
kgugala Dec 27, 2024
b12fba6
tb_top: toggle reset signal
kgugala Dec 27, 2024
eb1d39f
testbench: reconnect IC TAG mem
kgugala Dec 28, 2024
91d5abd
testbench: or reduce ME signal in IC_TAG macro
kgugala Dec 28, 2024
a1e25c1
testbench: add cpu halt test
kgugala Dec 28, 2024
8d67bd8
CI: run custom regression test in matrix
kgugala Dec 29, 2024
5bad895
testbench/hex: add csr_msecfg
kgugala Dec 29, 2024
2ebf40d
testbench/axi4_mux: drop timescale
kgugala Dec 29, 2024
67f9c38
Makefile: add axi4_mux files to TBFILES
kgugala Dec 29, 2024
9d19ae3
openocd_test: detect the simulation binary wait for common simulation…
kgugala Dec 29, 2024
0596ebc
utils.sh: use date for bash 4 compatibility
kgugala Dec 29, 2024
edb22bf
testbench: enable dmi core in all simulators
kgugala Dec 29, 2024
5186e9e
openocd_test: use diferent sim start strings for diferent binaries
kgugala Dec 29, 2024
5d7500c
CI: add custom openocd tests
kgugala Dec 29, 2024
692ed2e
gdb_test: set GCC_PREFIX is it is not set
kgugala Dec 29, 2024
9ff760c
test.gdb: drop failing memory accesses
kgugala Dec 29, 2024
d99fb40
gdb_test: chose proper sim binary and sim start string
kgugala Dec 29, 2024
64cff1e
sim_gdb: shorten sleep
kgugala Dec 29, 2024
5883d7e
cm.cfg drop axi_crossbar_wrap_2x1
kgugala Dec 29, 2024
49805a5
openocd/gdb test: update sim options
kgugala Dec 30, 2024
9983c50
openocd/gdb: gather more data
kgugala Dec 30, 2024
f129fb5
CI: merge Verilator reports and pass them to custom step
kgugala Dec 30, 2024
5d419e1
Bump verilator
RRozak Dec 30, 2024
6c435f9
axi memory: align address
wsipak Dec 31, 2024
c329ad9
Set coverage off on core_id
RRozak Dec 31, 2024
3b3844e
CI: generate data for coverview
kgugala Dec 30, 2024
File filter

Filter by extension

Filter by extension


Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
19 changes: 15 additions & 4 deletions .github/scripts/gdb_test.sh
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,9 @@

SIM_LOG=`realpath sim.log`
OPENOCD_LOG=`realpath openocd.log`
GCC_PREFIX=riscv64-unknown-elf
if [ -z $GCC_PREFIX ]; then
GCC_PREFIX=riscv64-unknown-elf
fi

# Ensure that RISC-V toolchain is installed
if ! which ${GCC_PREFIX}-gcc >/dev/null; then
Expand Down Expand Up @@ -58,13 +60,22 @@ echo -e "${COLOR_WHITE}======== Launching interactive simulation ========${COLOR

# Start the simulation
echo -e "Starting simulation..."
./obj_dir/Vtb_top >"${SIM_LOG}" 2>&1 &
if [ -f obj_dir/Vtb_top ]; then
SIM_START_STRING="VerilatorTB: Start of sim"
obj_dir/Vtb_top >"${SIM_LOG}" 2>&1 &
elif [ -f ./simv ]; then
SIM_START_STRING=" remote_bitbang_port 5000"
./simv +vcs+lic+wait -cm line+cond+fsm+tgl+branch >"${SIM_LOG}" 2>&1 &
else
echo "No simulation binary found, exiting"
exit 1
fi
SIM_PID=$!

# Wait
wait_for_phrase "${SIM_LOG}" "Start of sim"
wait_for_phrase "${SIM_LOG}" "${SIM_START_STRING}"
# TODO handle proper string in the output instead of waiting
sleep 10s
sleep 1s
retcode=$?
if [ $retcode -ne 0 ]; then
echo -e "${COLOR_RED}Failed to start the simulation: $retcode ${COLOR_OFF}"
Expand Down
13 changes: 11 additions & 2 deletions .github/scripts/openocd_test.sh
Original file line number Diff line number Diff line change
Expand Up @@ -42,11 +42,20 @@ echo -e "${COLOR_WHITE}======== Launching interactive simulation ========${COLOR

# Start the simulation
echo -e "Starting simulation..."
obj_dir/Vtb_top >"${SIM_LOG}" 2>&1 &
if [ -f obj_dir/Vtb_top ]; then
SIM_START_STRING="VerilatorTB: Start of sim"
obj_dir/Vtb_top >"${SIM_LOG}" 2>&1 &
elif [ -f ./simv ]; then
SIM_START_STRING=" remote_bitbang_port 5000"
./simv +vcs+lic+wait -cm line+cond+fsm+tgl+branch >"${SIM_LOG}" 2>&1 &
else
echo "No simulation binary found, exiting"
exit 1
fi
SIM_PID=$!

# Wait
wait_for_phrase "${SIM_LOG}" "VerilatorTB: Start of sim"
wait_for_phrase "${SIM_LOG}" "${SIM_START_STRING}"
if [ $? -ne 0 ]; then
echo -e "${COLOR_RED}Failed to start the simulation!${COLOR_OFF}"
print_logs
Expand Down
161 changes: 161 additions & 0 deletions .github/scripts/prepare_coverage_data.sh
Original file line number Diff line number Diff line change
@@ -0,0 +1,161 @@
set -e
set -o pipefail

cat <<EOF >> split.py
import sys
files = {}
active_file = None
with open(sys.argv[1], 'r') as file:
for line in file:
if line[0:1] == "#":
continue
elif line[0:3] == "SF:":
active_file = line.replace("\n", "").split(":")[1]
files[active_file] = {}
files[active_file]["da"] = []
files[active_file]["brda"] = []
files[active_file]["brf"] = 0
files[active_file]["brh"] = 0
elif line[0:3] == "DA:":
files[active_file]["da"].append(line.replace("\n", "").split(":")[1:])
elif line[0:5] == "BRDA:":
files[active_file]["brda"].append(line.replace("\n", "").split(":")[1:])
elif line[0:4] == "BRF:":
files[active_file]["brf"] = int(line.replace("\n", "").split(":")[1])
elif line[0:4] == "BRH:":
files[active_file]["brh"] = int(line.replace("\n", "").split(":")[1])
elif "end_of_record" in line:
active_file = None
if sys.argv[2] == "--branch":
print("TN:verilator_coverage")
for f in files:
print("SF:%s" % f)
for brda in files[f]["brda"]:
brda_line = brda[0].split(",")[0]
for da in files[f]["da"]:
da_line = da[0].split(",")[0]
if da_line == brda_line:
print("DA:%s" % (",".join(da)))
files[f]["da"].remove(da)
print("BRDA:%s" % (",".join(brda)))
print("end_of_record")
elif sys.argv[2] == "--line":
print("TN:verilator_coverage")
for f in files:
print("SF:%s" % f)
for da in files[f]["da"]:
da_line = da[0].split(",")[0]
found = False
for brda in files[f]["brda"]:
brda_line = brda[0].split(",")[0]
if da_line == brda_line:
found = True
if not found:
print("DA:%s" % (",".join(da)))
print("end_of_record")
sys.exit(0)
EOF

cat <<EOF >> preprocess.py
import sys
filter = None
in_file = False
if sys.argv[2] == "--filter":
filter = sys.argv[3]
print("TN:verilator_coverage")
with open(sys.argv[1], 'r') as file:
for line in file:
line = line.replace("\n", "")
if line[0:3] == "SF:":
if filter == None or line.startswith("SF:%s" % filter):
in_file = True
print(line)
continue
else:
in_file = False
continue
if not in_file:
continue
if "end_of_record" in line:
in_file = False
print(line)
continue
if line[0:1] == "#":
print(line)
elif line[0:3] == "DA:":
data = line.split(",")
line = "%s,%d" % (data[0], int(data[1]) > 0)
print(line)
elif line[0:5] == "BRDA:":
data = line.split(",")
line = "%s,%s,%s,%d" % (data[0],data[1],data[2], int(data[3]) > 0)
print(line)
else:
print(line)
EOF

mkdir info_files
mv *.info info_files
cd info_files
git clone https://github.com/linux-test-project/lcov -b v2.3-beta
PATH="`pwd`/lcov/bin:$PATH"

ls *_toggle.info | xargs printf -- '-a %s\n' | xargs echo | awk '{ print "lcov "$0" --ignore-errors inconsistent --rc lcov_branch_coverage=1 -o coverage_toggle_verilator.info" }' | bash
ls *_branch.info | xargs printf -- '-a %s\n' | xargs echo | awk '{ print "lcov "$0" --ignore-errors inconsistent --rc lcov_branch_coverage=1 -o coverage_line_verilator.info" }' | bash

cp coverage_toggle_verilator.info ../
cp coverage_line_verilator.info ../

cd ../
rm -rf info_files

mv coverage_line_verilator.info line.info
python3 split.py line.info --branch > coverage_branch_verilator.info
python3 split.py line.info --line > coverage_line_verilator.info

find . -type f -name 'coverage_*.info' -exec sed -i 's_^SF:.*Cores-VeeR-EL2/_SF:_g' {} \;

python3 preprocess.py coverage_line_verilator.info --filter "design/" > _coverage_line.info
python3 preprocess.py coverage_toggle_verilator.info --filter "design/" > _coverage_toggle.info
python3 preprocess.py coverage_branch_verilator.info --filter "design/" > _coverage_branch.info

cp _coverage_line.info coverage_line_verilator.info
cp _coverage_branch.info coverage_branch_verilator.info
cp _coverage_toggle.info coverage_toggle_verilator.info

grep 'SF:' coverage_*.info | cut -d ":" -f 3 | sort | uniq > files.txt

export BRANCH=$GITHUB_HEAD_REF
export COMMIT=$GITHUB_SHA
{
while read file
do
if [ -f $file ]; then
echo "### FILE: $file"
cat "$file"
else
echo "### SKIPPING: $file"
fi
done
} < files.txt > sources.txt

mkdir test_data
cp coverage_line_*.info coverage_toggle_*.info coverage_branch_* sources.txt test_data

# add logo
cp docs/dashboard-styles/assets/chips-alliance-logo-mono.svg test_data/logo.svg

# add config.json
echo -n '{ "datasets": { "verilator": { "line": "coverage_line_verilator.info", "branch": "coverage_branch_verilator.info", "toggle": "coverage_toggle_verilator.info" } }, "title": "VeeR EL2 coverage dashboard", "commit": "' > test_data/config.json
echo -n $COMMIT >> test_data/config.json
echo -n '", "branch": "' >> test_data/config.json
echo -n $BRANCH >> test_data/config.json
echo -n '", "repo": "cores-veer-el2", "timestamp": "' >> test_data/config.json
echo -n `date +"%Y-%m-%dT%H:%M:%S.%3N%z"` >> test_data/config.json
echo -n '" }' >> test_data/config.json

cat test_data/config.json

cd test_data
zip ../data.zip *
cd ..
14 changes: 0 additions & 14 deletions .github/scripts/test.gdb
Original file line number Diff line number Diff line change
Expand Up @@ -126,19 +126,5 @@ continue

delete

# This causes an error. Let's execute it anyway for coverage.
echo Accessing region at 0xe0000000...\n
set *(0xe0000000) = 0x01234567
set *(0xe0000004) = 0x89ABCDEF
set *(0xe0000008) = 0x55555555
set *(0xe000000C) = 0xAAAAAAAA
print/x *0xe0000000@4
echo Accessing region at 0xf0000000...\n
set *(0xf0000000) = 0x01234567
set *(0xf0000004) = 0x89ABCDEF
set *(0xf0000008) = 0x55555555
set *(0xf000000C) = 0xAAAAAAAA
print/x *0xf0000000@4

# end the simulation gracefully
set *(volatile unsigned char*)0xd0580000 = 0xff
4 changes: 2 additions & 2 deletions .github/scripts/utils.sh
Original file line number Diff line number Diff line change
Expand Up @@ -33,8 +33,8 @@ wait_for_phrase () {
fi

# Wait for the phrase
DEADLINE=$((${EPOCHSECONDS} + 30))
while [ ${EPOCHSECONDS} -lt ${DEADLINE} ]
DEADLINE=$(($(date +%s) + 30))
while [ $(date +%s) -lt ${DEADLINE} ]
do
# Check for the phrase
grep "$2" "$1" >/dev/null
Expand Down
8 changes: 8 additions & 0 deletions .github/workflows/publish-webpage.yml
Original file line number Diff line number Diff line change
Expand Up @@ -69,6 +69,7 @@ jobs:
- name: Update webpage
if: github.event_name != 'pull_request'
run: |
mv coverage_dashboard/*.zip .
sis -d webpage \
--include-documentation \
--doc-project-name "Cores VeeR EL2" \
Expand All @@ -79,11 +80,15 @@ jobs:
rm -rf public.new/html/main/docs_rendered
mkdir -p public.new/html/main/docs_rendered
mv ./docs_rendered/* public.new/html/main/docs_rendered
mv data.zip public.new/html/main/
mv data_v.zip public.new/html/main/
echo ${GITHUB_RUN_ID} > public.new/html/main/run_id
tar -acf webpage.tar.gz public.new

- name: Update webpage PR
if: github.event_name == 'pull_request'
run: |
mv coverage_dashboard/*.zip .
sis -d webpage \
--include-documentation \
--doc-project-name "Cores VeeR EL2" \
Expand All @@ -94,6 +99,9 @@ jobs:
rm -rf public.new/html/dev/${{ github.event.number }}/docs_rendered
mkdir -p public.new/html/dev/${{ github.event.number }}/docs_rendered
mv ./docs_rendered/* public.new/html/dev/${{ github.event.number }}/docs_rendered
mv data.zip public.new/html/dev/${{ github.event.number }}/
mv data_v.zip public.new/html/dev/${{ github.event.number }}/
echo ${GITHUB_RUN_ID} > public.new/html/dev/${{ github.event.number }}/run_id
tar -acf webpage.tar.gz public.new

- name: Add redirect index page
Expand Down
Loading
Loading