Code

Add cm config#303

Code

Merged

kgugala merged 27 commits intomainchipsalliance/Cores-VeeR-EL2:mainfrom cm-cfgchipsalliance/Cores-VeeR-EL2:cm-cfgCopy head branch name to clipboardJan 1, 2025

+729-65

Commits

Commits on Dec 27, 2024

• Add cm config

  kgugala

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  1e00195

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• waive rst_vec and nmi_vec signals

  kgugala

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• tb_top: toggle reset signal

  kgugala

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Commits on Dec 28, 2024

• testbench: reconnect IC TAG mem

  kgugala

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• testbench: or reduce ME signal in IC_TAG macro

  kgugala

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• testbench: add cpu halt test

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Commits on Dec 29, 2024

• CI: run custom regression test in matrix

  kgugala

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• testbench/hex: add csr_msecfg

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• testbench/axi4_mux: drop timescale

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• Makefile: add axi4_mux files to TBFILES

  kgugala

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• openocd_test: detect the simulation binary wait for common simulation log line

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• utils.sh: use date for bash 4 compatibility

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• testbench: enable dmi core in all simulators

  kgugala

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• openocd_test: use diferent sim start strings for diferent binaries

  kgugala

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• CI: add custom openocd tests

  kgugala

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• gdb_test: set GCC_PREFIX is it is not set

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• test.gdb: drop failing memory accesses

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• gdb_test: chose proper sim binary and sim start string

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• sim_gdb: shorten sleep

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• cm.cfg drop axi_crossbar_wrap_2x1

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Commits on Dec 30, 2024

• openocd/gdb test: update sim options

  kgugala

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• openocd/gdb: gather more data

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• CI: merge Verilator reports and pass them to custom step

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Commits on Jan 1, 2025

• Bump verilator

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  RRozak

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  kgugala

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• axi memory: align address

  

  wsipak

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  kgugala

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• Set coverage off on core_id

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  RRozak

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  kgugala

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• CI: generate data for coverview

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