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test lsu_bus_buffer #289
test lsu_bus_buffer #289
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Links to coverage and verification reports for this PR (#289) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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Links to coverage and verification reports for this PR (#289) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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Links to coverage and verification reports for this PR (#289) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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Links to coverage and verification reports for this PR (#289) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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Links to coverage and verification reports for this PR (#289) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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The signal is currently tied to `1`. Let's export it to the C++ testbench so that we can manipulate it there.
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Links to coverage and verification reports for this PR (#289) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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LGTM
This modifies the testbench to test the part in
lsu_bus_buffer
which depends onlsu_bus_clk_en
signal currently tied to1
.Currently this state is never reached.
The testbench already has code to perform pre-operation resets and checks. Let's extend this part to let the core run with
lsu_bus_clk_en
being 10 times slower thancore_clk
, which makes the buffer reach the previously unreached state.