tb: control rst_l

chipsalliance · Dec 13, 2024 · 694bf82 · 694bf82
1 parent c6087c0
commit 694bf82
Show file tree

Hide file tree

Showing 2 changed files with 17 additions and 2 deletions.
diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv
@@ -28,6 +28,7 @@ module tb_top
     `include "el2_param.vh"
 ) (
     input bit                   core_clk,
+    input bit                   rst_l,
     input bit [31:0]            mem_signature_begin,
     input bit [31:0]            mem_signature_end,
     input bit [31:0]            mem_mailbox,
@@ -100,7 +101,6 @@ module tb_top
     bit          [31:0]         mem_signature_end   = 32'd0;
     bit          [31:0]         mem_mailbox         = 32'hD0580000;
 `endif
-    logic                       rst_l;
     logic                       porst_l;
     logic [pt.PIC_TOTAL_INT:1]  ext_int;
     logic                       nmi_int;
@@ -1011,7 +1011,6 @@ module tb_top
     end
 
 
-    assign rst_l = cycleCnt > 5;
     assign porst_l = cycleCnt > 2;
 
    //=========================================================================-

diff --git a/testbench/test_tb_top.cpp b/testbench/test_tb_top.cpp
@@ -147,6 +147,14 @@ int main(int argc, char** argv) {
   tb->trace (tfp, 24);
   tfp->open ("sim.vcd");
 #endif
+  // reset
+  tb->rst_l = 0;
+  for (int i=0;i<6;i++) {
+    main_time += 5;
+    tb->core_clk = !tb->core_clk;
+    tb->eval();
+  }
+  tb->rst_l = 1;
   // Simulate
   if(test_halt) {
     // Test halt/start first (if requested)
@@ -243,6 +251,14 @@ int main(int argc, char** argv) {
       tb->core_clk = !tb->core_clk;
       tb->eval();
     }
+    // reset
+    tb->rst_l = 0;
+    for (int i=0;i<6;i++) {
+      main_time += 5;
+      tb->core_clk = !tb->core_clk;
+      tb->eval();
+    }
+    tb->rst_l = 1;
   } else {
     tb->i_cpu_halt_req = 0;
     tb->i_cpu_run_req = 0;