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bug fix
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Andrea Bettati committed Dec 23, 2019
1 parent 3062088 commit cbc1a87
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Showing 42 changed files with 517 additions and 458 deletions.
24 changes: 0 additions & 24 deletions rtl/include/riscv_defines.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -416,30 +416,6 @@ parameter EXC_CAUSE_STORE_FAULT = 6'h07;
parameter EXC_CAUSE_ECALL_UMODE = 6'h08;
parameter EXC_CAUSE_ECALL_MMODE = 6'h0B;


// Possible irq ids
typedef enum logic [4:0] {
NMI_IRQ_ID = 5'd31,
FAST14_IRQ_ID = 5'd30,
FAST13_IRQ_ID = 5'd29,
FAST12_IRQ_ID = 5'd28,
FAST11_IRQ_ID = 5'd27,
FAST10_IRQ_ID = 5'd26,
FAST9_IRQ_ID = 5'd25,
FAST8_IRQ_ID = 5'd24,
FAST7_IRQ_ID = 5'd23,
FAST6_IRQ_ID = 5'd22,
FAST5_IRQ_ID = 5'd21,
FAST4_IRQ_ID = 5'd20,
FAST3_IRQ_ID = 5'd19,
FAST2_IRQ_ID = 5'd18,
FAST1_IRQ_ID = 5'd17,
FAST0_IRQ_ID = 5'd16,
EXTERNAL_IRQ_ID = 5'd11,
TIMER_IRQ_ID = 5'd07,
SOFTWARE_IRQ_ID = 5'd03
} irq_id_e;

// Interrupt lines struct
typedef struct packed {
logic irq_software;
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39 changes: 20 additions & 19 deletions rtl/riscv_cs_registers.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -277,6 +277,7 @@ module riscv_cs_registers
Interrupts_t mip;
Masked_Interrupts_t mie_q, mie_n;


logic is_irq;
PrivLvl_t priv_lvl_n, priv_lvl_q, priv_lvl_reg_q;
Pmp_t pmp_reg_q, pmp_reg_n;
Expand Down Expand Up @@ -983,36 +984,36 @@ end //PULP_SECURE
// TODO abet insert nmi_mode_q?
if (mip.irq_nmi) begin
// EXC_CAUSE_IRQ_NM
irq_id_o = NMI_IRQ_ID;
irq_id_o = {5'd31};

end else if(mip.irq_fast != '0)
begin
if (mip.irq_fast[14]) irq_id_o = FAST14_IRQ_ID;
else if (mip.irq_fast[13]) irq_id_o = FAST13_IRQ_ID;
else if (mip.irq_fast[12]) irq_id_o = FAST12_IRQ_ID;
else if (mip.irq_fast[11]) irq_id_o = FAST11_IRQ_ID;
else if (mip.irq_fast[10]) irq_id_o = FAST10_IRQ_ID;
else if (mip.irq_fast[ 9]) irq_id_o = FAST9_IRQ_ID;
else if (mip.irq_fast[ 8]) irq_id_o = FAST8_IRQ_ID;
else if (mip.irq_fast[ 7]) irq_id_o = FAST7_IRQ_ID;
else if (mip.irq_fast[ 6]) irq_id_o = FAST6_IRQ_ID;
else if (mip.irq_fast[ 5]) irq_id_o = FAST5_IRQ_ID;
else if (mip.irq_fast[ 4]) irq_id_o = FAST4_IRQ_ID;
else if (mip.irq_fast[ 3]) irq_id_o = FAST3_IRQ_ID;
else if (mip.irq_fast[ 2]) irq_id_o = FAST2_IRQ_ID;
else if (mip.irq_fast[ 1]) irq_id_o = FAST1_IRQ_ID;
else irq_id_o = FAST0_IRQ_ID;
if (mip.irq_fast[14]) irq_id_o = 5'd30;
else if (mip.irq_fast[13]) irq_id_o = 5'd29;
else if (mip.irq_fast[12]) irq_id_o = 5'd28;
else if (mip.irq_fast[11]) irq_id_o = 5'd27;
else if (mip.irq_fast[10]) irq_id_o = 5'd26;
else if (mip.irq_fast[ 9]) irq_id_o = 5'd25;
else if (mip.irq_fast[ 8]) irq_id_o = 5'd24;
else if (mip.irq_fast[ 7]) irq_id_o = 5'd23;
else if (mip.irq_fast[ 6]) irq_id_o = 5'd22;
else if (mip.irq_fast[ 5]) irq_id_o = 5'd21;
else if (mip.irq_fast[ 4]) irq_id_o = 5'd20;
else if (mip.irq_fast[ 3]) irq_id_o = 5'd19;
else if (mip.irq_fast[ 2]) irq_id_o = 5'd18;
else if (mip.irq_fast[ 1]) irq_id_o = 5'd17;
else irq_id_o = 5'd16;
end else if (mip.irq_external) begin
// EXC_CAUSE_IRQ_EXTERNAL_M
irq_id_o = EXTERNAL_IRQ_ID;
irq_id_o = {5'd11};

end else if (mip.irq_software) begin
// EXC_CAUSE_IRQ_SOFTWARE_M;
irq_id_o = SOFTWARE_IRQ_ID;
irq_id_o = {5'd03};

end else begin // mip.irq_timer
// EXC_CAUSE_IRQ_TIMER_M;
irq_id_o = TIMER_IRQ_ID;
irq_id_o = {5'd07};
end
end

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4 changes: 2 additions & 2 deletions tb/core/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -249,7 +249,7 @@ interrupt_test/interrupt_test.elf: interrupt_test/interrupt_test.c
-T interrupt_test/link.ld \
-static \
interrupt_test/crt0.S \
$^ interrupt_test/syscalls.c custom/vectors.S \
$^ interrupt_test/syscalls.c interrupt_test/vectors.S \
-I $(RISCV)/riscv32-unknown-elf/include \
-L $(RISCV)/riscv32-unknown-elf/lib \
-lc -lm -lgcc
Expand Down Expand Up @@ -452,7 +452,7 @@ csmith-loop: riscv-fesvr/build.ok riscv-isa-sim/build.ok

# general targets
.PHONY: clean
clean: tb-clean verilate-clean vcs-clean firmware-clean csmith-clean custom-clean
clean: tb-clean verilate-clean vcs-clean firmware-clean csmith-clean custom-clean interrupt-clean

.PHONY: distclean
distclean: clean
Expand Down
Binary file modified tb/core/cobj_dir/Vtb_top_verilator
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Binary file not shown.
12 changes: 6 additions & 6 deletions tb/core/cobj_dir/Vtb_top_verilator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -8730,7 +8730,7 @@ void Vtb_top_verilator::_settle__TOP__2(Vtb_top_verilator__Syms* __restrict vlSy
= (3U & ((IData)(vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__mulh_active)
? (IData)(vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__mulh_subword)
: VL_NEGATE_I((IData)((IData)(vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__mult_sel_subword_ex)))));
vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT____Vcellout__cs_registers_i__irq_id_o
vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_id
= ((1U & vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip)
? 0x1fU : ((0U != (0x7fffU & (vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip
>> 1U))) ?
Expand Down Expand Up @@ -8786,7 +8786,7 @@ void Vtb_top_verilator::_settle__TOP__2(Vtb_top_verilator__Syms* __restrict vlSy
: 0x10U))))))))))))))
: ((0x10000U & vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip)
? 0xbU : ((0x40000U & vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip)
? 7U : 3U))));
? 3U : 7U))));
vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_pending
= (1U & (((((vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip
>> 0x12U) | (vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip
Expand Down Expand Up @@ -25677,7 +25677,7 @@ VL_INLINE_OPT void Vtb_top_verilator::_sequent__TOP__6(Vtb_top_verilator__Syms*
& (IData)(vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_pending))) {
__Vdly__tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__int_controller_i__DOT__exc_ctrl_cs = 1U;
vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__int_controller_i__DOT__irq_id_q
= vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT____Vcellout__cs_registers_i__irq_id_o;
= vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_id;
vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__int_controller_i__DOT__irq_sec_q = 0U;
}
} else {
Expand Down Expand Up @@ -27878,7 +27878,7 @@ VL_INLINE_OPT void Vtb_top_verilator::_sequent__TOP__6(Vtb_top_verilator__Syms*
= (3U & ((IData)(vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__mulh_active)
? (IData)(vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__mulh_subword)
: VL_NEGATE_I((IData)((IData)(vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__mult_sel_subword_ex)))));
vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT____Vcellout__cs_registers_i__irq_id_o
vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_id
= ((1U & vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip)
? 0x1fU : ((0U != (0x7fffU & (vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip
>> 1U))) ?
Expand Down Expand Up @@ -27934,7 +27934,7 @@ VL_INLINE_OPT void Vtb_top_verilator::_sequent__TOP__6(Vtb_top_verilator__Syms*
: 0x10U))))))))))))))
: ((0x10000U & vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip)
? 0xbU : ((0x40000U & vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip)
? 7U : 3U))));
? 3U : 7U))));
vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_pending
= (1U & (((((vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip
>> 0x12U) | (vlTOPp->tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__mip
Expand Down Expand Up @@ -51303,8 +51303,8 @@ void Vtb_top_verilator::_ctor_var_reset() {
tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__instr_req_pmp = VL_RAND_RESET_I(1);
tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__instr_gnt_pmp = VL_RAND_RESET_I(1);
tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_pending = VL_RAND_RESET_I(1);
tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_id = VL_RAND_RESET_I(5);
tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__clk = VL_RAND_RESET_I(1);
tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT____Vcellout__cs_registers_i__irq_id_o = VL_RAND_RESET_I(5);
tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__mult_is_clpx_ex = VL_RAND_RESET_I(1);
tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__core_clock_gate_i__DOT__clk_en = VL_RAND_RESET_I(1);
tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__offset_fsm_cs = VL_RAND_RESET_I(1);
Expand Down
16 changes: 8 additions & 8 deletions tb/core/cobj_dir/Vtb_top_verilator.h
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Original file line number Diff line number Diff line change
Expand Up @@ -121,6 +121,7 @@ VL_MODULE(Vtb_top_verilator) {
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__instr_req_pmp;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__instr_gnt_pmp;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_pending;
CData/*4:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__irq_id;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__mult_is_clpx_ex;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__core_clock_gate_i__DOT__clk_en;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__offset_fsm_cs;
Expand Down Expand Up @@ -160,9 +161,9 @@ VL_MODULE(Vtb_top_verilator) {
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__illegal_insn_dec;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__ebrk_insn;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__mret_insn_dec;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__uret_insn_dec;
};
struct {
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__uret_insn_dec;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__dret_insn_dec;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__ecall_insn_dec;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__pipe_flush_dec;
Expand Down Expand Up @@ -226,9 +227,9 @@ VL_MODULE(Vtb_top_verilator) {
CData/*1:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__alu_vec_mode;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__scalar_replication;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__reg_d_ex_is_reg_a_id;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__reg_d_ex_is_reg_b_id;
};
struct {
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__reg_d_ex_is_reg_b_id;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__reg_d_ex_is_reg_c_id;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__reg_d_wb_is_reg_a_id;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__reg_d_alu_is_reg_a_id;
Expand Down Expand Up @@ -292,9 +293,9 @@ VL_MODULE(Vtb_top_verilator) {
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__div_ready;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__int_div__DOT__div_op_a_signed;
IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__alu_popcnt_i__DOT__cnt_l1;
IData/*23:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__alu_popcnt_i__DOT__cnt_l2;
};
struct {
IData/*23:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__alu_popcnt_i__DOT__cnt_l2;
SData/*15:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__alu_popcnt_i__DOT__cnt_l3;
SData/*9:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__alu_popcnt_i__DOT__cnt_l4;
WData/*159:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__alu_ff_i__DOT__index_lut[5];
Expand Down Expand Up @@ -358,9 +359,9 @@ VL_MODULE(Vtb_top_verilator) {
CData/*1:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__ram_i__DOT__select_rdata_d;
CData/*1:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__ram_i__DOT__select_rdata_q;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__ram_i__DOT__transaction;
CData/*1:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__ram_i__DOT__state_valid_n;
};
struct {
CData/*1:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__ram_i__DOT__state_valid_n;
CData/*1:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__ram_i__DOT__state_valid_q;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__ram_i__DOT__data_rvalid_q;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__ram_i__DOT__instr_rvalid_q;
Expand Down Expand Up @@ -424,9 +425,9 @@ VL_MODULE(Vtb_top_verilator) {
IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__genblk1__DOT__prefetch_128__DOT__prefetch_buffer_i__DOT__rdata_last_q;
IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__genblk1__DOT__prefetch_128__DOT__prefetch_buffer_i__DOT__rdata;
IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__genblk1__DOT__prefetch_128__DOT__prefetch_buffer_i__DOT__rdata_unaligned;
WData/*127:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__genblk1__DOT__prefetch_128__DOT__prefetch_buffer_i__DOT__L0_buffer_i__DOT__L0_buffer[4];
};
struct {
WData/*127:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__genblk1__DOT__prefetch_128__DOT__prefetch_buffer_i__DOT__L0_buffer_i__DOT__L0_buffer[4];
IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__genblk1__DOT__prefetch_128__DOT__prefetch_buffer_i__DOT__L0_buffer_i__DOT__addr_q;
IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__genblk1__DOT__prefetch_128__DOT__prefetch_buffer_i__DOT__L0_buffer_i__DOT__instr_addr_int;
IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__id_stage_i__DOT__imm_i_type;
Expand Down Expand Up @@ -490,9 +491,9 @@ VL_MODULE(Vtb_top_verilator) {
IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__int_div__DOT__div_i__DOT__BReg_DP;
IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__int_div__DOT__div_i__DOT__BReg_DN;
IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__int_div__DOT__div_i__DOT__AddMux_D;
IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__int_div__DOT__div_i__DOT__AddTmp_D;
};
struct {
IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__int_div__DOT__div_i__DOT__AddTmp_D;
IData/*31:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__int_div__DOT__div_i__DOT__OutMux_D;
IData/*16:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__short_op_a;
IData/*16:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__short_op_b;
Expand Down Expand Up @@ -556,9 +557,9 @@ VL_MODULE(Vtb_top_verilator) {
QData/*36:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__alu_i__DOT__adder_result_expanded;
QData/*33:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__short_mac;
QData/*33:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__short_result;
QData/*32:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__dot_short_result;
};
struct {
QData/*32:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__dot_short_result;
WData/*67:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__ex_stage_i__DOT__mult_i__DOT__genblk1__DOT__dot_short_mul[3];
WData/*767:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__pmp_reg_q[24];
WData/*767:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT__pmp_reg_n[24];
Expand All @@ -568,7 +569,6 @@ VL_MODULE(Vtb_top_verilator) {

// LOCAL VARIABLES
// Internals; generally not touched by application code
CData/*4:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT____Vcellout__cs_registers_i__irq_id_o;
CData/*1:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT____Vcellinp__hwloop_controller_i__hwlp_dec_cnt_id_i;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__if_stage_i__DOT__genblk1__DOT__prefetch_128__DOT__prefetch_buffer_i__DOT____Vcellinp__L0_buffer_i__hwlp_i;
CData/*0:0*/ tb_top_verilator__DOT__riscv_wrapper_i__DOT__riscv_core_i__DOT__cs_registers_i__DOT____Vlvbound2;
Expand Down
Binary file modified tb/core/cobj_dir/Vtb_top_verilator__ALL.a
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