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Add $check
cell to represent assertions with messages
#4128
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Just leaving a note that |
You mentioned that you would be able to do this--is that still the case? |
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Just occurred to me, so noting it down: we need to visit |
Done |
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From my point of view this PR is done, though of course it breaks formal flows, and the tests that are looking for formal flow cells don't pass. |
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My branch with the necessary yosys changes to keep the FV flows working by handling The corresponding changes on the SBY side are at YosysHQ/sby#259 which keeps all SBY tests passing when using the yosys from my |
Fantastic work! Thank you @jix. I'll take a look at the final test failure, probably, tomorrow. |
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I've updated the PR to not emit an assertion message in the Verilog frontend and to ignore empty message in the Verilog backend; and to check for non-unique names of procedural assertions. I think that's all! |
There are a few failures of the kind:
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Ah I missed the tests that end up using |
$check
cell to represent assertions with messages$check
cell to represent assertions with messages
@whitequark I can have a final look-over tomorrow. |
Thanks, that would be great. |
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I went through all of it, only skipped some of the CXXRTL bits, and other than the things I commented on nothing jumped at me.
This compares the write_smt2 output pretty much verbatim, which contains auto generated private names and fixes an arbitrary ordering. The tested functionality is also covered by SBY tests which actually interpret the write_smt2 output using an SMT solver and thus are much more robust, so we can safely remove this test.
Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions.
This adds support for `$check` cells in chformal and adds a `-lower` mode which converts `$check` cells into `$assert` etc. cells with a `$print` cell to output the `$check` message.
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This should address everything @povik brought up during review and also adds some tests that would have detected the issues with the now fixed clk2fflogic code and now also passes all tests on CI including the SBY tests.
I'll do the honors. |
cell->setPort(ID::EN, module->And(NEW_ID, sig_en_sampled, sig_trg_combined)); | ||
cell->setPort(ID::ARGS, sig_args_sampled); | ||
if (cell->type == ID($check)) { | ||
SigBit sig_a_sampled = sample_data(module, sig_en, State::S1, false, false).sampled; |
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Should be sampling sig_a
Relates to #4143.