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473 Open 1,330 Closed
473 Open 1,330 Closed
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Issues list

async2sync fails on check cells with async reset pending-verification This issue is pending verification and/or reproduction
#4875 opened Jan 29, 2025 by georgerennie
CXXRTL should warn or fail on unsupported clock features bug cxxrtl
#4874 opened Jan 29, 2025 by povik
4
Yosys will sometimes emit a flip-flop that never toggles instead of a constant 0 pending-verification This issue is pending verification and/or reproduction
#4872 opened Jan 28, 2025 by leocassarani
Support for multi-line string for system verilog feature-request SystemVerilog Issues and questions related to SystemVerilog
#4871 opened Jan 28, 2025 by KelvinChung2000
Lexer prints token to stdout when multi-line string is attempted to be used bug
#4870 opened Jan 28, 2025 by widlarizer
1
Yosys synth_ice40 -dsp fails on an assertion bug
#4865 opened Jan 23, 2025 by zapta
2
Test
#4862 opened Jan 21, 2025 by ShinyKate
Fail to detect FSM with specific writing style bug
#4861 opened Jan 21, 2025 by KelvinChung2000
2
synth failure pending-verification This issue is pending verification and/or reproduction
#4844 opened Jan 14, 2025 by FSY369
@povik
10
Support gziped Liberty files feature-request
#4830 opened Jan 1, 2025 by hpretl
1
@widlarizer
16
Inconsistent simulation before and after synthesis of complex assignment expressions pending-verification This issue is pending verification and/or reproduction
#4828 opened Dec 24, 2024 by FSY369
12
Built yosys.wasm is too large needs-info Issue needs more context/information in order to be resolved pending-verification This issue is pending verification and/or reproduction
#4822 opened Dec 18, 2024 by LSTM-Kirigaya
1
Add an optional yosys start script feature-request
#4820 opened Dec 16, 2024 by widlarizer
1
synth_xilinx error in simple demo bug
#4816 opened Dec 13, 2024 by lehaifeng000
3
Deviation Between Yosys RTLIL EBNF Docs and RTLIL Lex/Yacc Frontend pending-verification This issue is pending verification and/or reproduction
#4811 opened Dec 10, 2024 by ThePerfectComputer
5
Synthesis with -nowidelut gives drastically better results pending-verification This issue is pending verification and/or reproduction
#4798 opened Dec 5, 2024 by t-wallet
1
techmap should warn when CONSTMSK/CONSTVAL are used with a nonexistent port feature-request
#4795 opened Dec 3, 2024 by Ravenslofty
Preservation of signedness flag on attribute values inconsistent pending-verification This issue is pending verification and/or reproduction
#4793 opened Dec 2, 2024 by povik
read_verilog gives multiple drivers to variables initialized both in declaration and initial pending-verification This issue is pending verification and/or reproduction
#4792 opened Dec 2, 2024 by widlarizer
cxxrtl output port changes value after back to back .step() bug cxxrtl
#4786 opened Nov 29, 2024 by rroohhh
4
read_verilog: array of instances parsing assertion failure pending-verification This issue is pending verification and/or reproduction
#4785 opened Nov 29, 2024 by Muxianesty
1
Verilog: Mixing integer and real values causes error pending-verification This issue is pending verification and/or reproduction
#4780 opened Nov 28, 2024 by flafflar
2
Docs issues for offline pdf builds pending-verification This issue is pending verification and/or reproduction
#4777 opened Nov 28, 2024 by KrystalDelusion
Error: Abc_CommandAbc9If(): Mapping of GIA has failed. pending-verification This issue is pending verification and/or reproduction
#4766 opened Nov 24, 2024 by spth
1
Measure global_id_index_ construction overhead feature-request
#4761 opened Nov 20, 2024 by widlarizer
ProTip! no:milestone will show everything without a milestone.