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Issues list

Preservation of signedness flag on attribute values inconsistent pending-verification This issue is pending verification and/or reproduction
#4793 opened Dec 2, 2024 by povik
tee -q -o <bad-path> fails silently pending-verification This issue is pending verification and/or reproduction
#4636 opened Oct 7, 2024 by povik
Verilog asynchronous reset pattern leads to corrupted $check, $print control signals pending-verification This issue is pending verification and/or reproduction
#4231 opened Feb 23, 2024 by povik
memory_collect makes up priority relationships between two $memwr pending-verification This issue is pending verification and/or reproduction
#4196 opened Feb 9, 2024 by povik
Verific doesn't represent write port priority pending-verification This issue is pending verification and/or reproduction
#4195 opened Feb 9, 2024 by povik
sim doesn't consider assertions failed if EN=x A=0 pending-verification This issue is pending verification and/or reproduction
#4092 opened Dec 21, 2023 by povik
Async reset inference ignores process switch polarity pending-verification This issue is pending verification and/or reproduction
#4076 opened Dec 14, 2023 by povik
Split off evaluable/combinational flags in celltypes.h pending-verification This issue is pending verification and/or reproduction
#4034 opened Nov 16, 2023 by povik
Celltype $alu is marked evaluable but misses eval implementation pending-verification This issue is pending verification and/or reproduction
#3913 opened Sep 4, 2023 by povik
Suboptimal default synthesis of $bmux, $shiftx pending-verification This issue is pending verification and/or reproduction
#3893 opened Aug 16, 2023 by povik
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