Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

lattice: Fix mapping onto DP8KC for data width 1 or 2 #4087

Merged
merged 2 commits into from
Dec 21, 2023
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 4 additions & 0 deletions techlibs/lattice/brams_8kc.txt
Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,10 @@ ram block $__PDPW8KC_ {
cost 64;
init no_undef;
port sr "R" {
# width 2 cannot be supported because of quirks
# of the primitive, and memlib requires us to
# remove width 1 as well
width 4 9 18;
clock posedge;
clken;
option "RESETMODE" "SYNC" {
Expand Down
16 changes: 14 additions & 2 deletions techlibs/lattice/brams_map_8kc.v
Original file line number Diff line number Diff line change
Expand Up @@ -38,8 +38,20 @@ endfunction

wire [8:0] DOA;
wire [8:0] DOB;
wire [8:0] DIA = PORT_A_WR_DATA;
wire [8:0] DIB = PORT_B_WR_DATA;
wire [8:0] DIA;
wire [8:0] DIB;

case(PORT_A_WIDTH)
1: assign DIA = {7'bx, PORT_A_WR_DATA[0], 1'bx};
2: assign DIA = {3'bx, PORT_A_WR_DATA[1], 2'bx, PORT_A_WR_DATA[0], 2'bx};
default: assign DIA = PORT_A_WR_DATA;
endcase

case(PORT_B_WIDTH)
1: assign DIB = {7'bx, PORT_B_WR_DATA[0], 1'bx};
2: assign DIB = {3'bx, PORT_B_WR_DATA[1], 2'bx, PORT_B_WR_DATA[0], 2'bx};
default: assign DIB = PORT_B_WR_DATA;
endcase

assign PORT_A_RD_DATA = DOA;
assign PORT_B_RD_DATA = DOB;
Expand Down
Loading