Skip to content

Commit

Permalink
yosys-witness: Add aiw2yw --present-only to omit unused signals
Browse files Browse the repository at this point in the history
  • Loading branch information
jix committed Dec 14, 2023
1 parent 3fab4d4 commit 94d7c22
Showing 1 changed file with 41 additions and 12 deletions.
53 changes: 41 additions & 12 deletions backends/smt2/witness.py
Original file line number Diff line number Diff line change
Expand Up @@ -183,7 +183,8 @@ def __init__(self, mapfile):
@click.argument("mapfile", type=click.File("r"))
@click.argument("output", type=click.File("w"))
@click.option("--skip-x", help="Leave input x bits unassigned.", is_flag=True)
def aiw2yw(input, mapfile, output, skip_x):
@click.option("--present-only", help="Only include bits present in at least one time step.", is_flag=True)
def aiw2yw(input, mapfile, output, skip_x, present_only):
input_name = input.name
click.echo(f"Converting AIGER witness trace {input_name!r} to Yosys witness trace {output.name!r}...")
click.echo(f"Using Yosys witness AIGER map file {mapfile.name!r}")
Expand Down Expand Up @@ -211,16 +212,23 @@ def aiw2yw(input, mapfile, output, skip_x):
if not re.match(r'[0]*$', ffline):
raise click.ClickException(f"{input_name}: non-default initial state not supported")

outyw = WriteWitness(output, 'yosys-witness aiw2yw')
if not present_only:
outyw = WriteWitness(output, "yosys-witness aiw2yw")

for clock in aiger_map.clocks:
outyw.add_clock(clock["path"], clock["offset"], clock["edge"])
for clock in aiger_map.clocks:
outyw.add_clock(clock["path"], clock["offset"], clock["edge"])

for (path, offset), id in aiger_map.sigmap.bit_to_id.items():
outyw.add_sig(path, offset, init_only=id in aiger_map.init_inputs)
for (path, offset), id in aiger_map.sigmap.bit_to_id.items():
outyw.add_sig(path, offset, init_only=id in aiger_map.init_inputs)

missing = set()
seen = set()

buffered_steps = []

skip = "x?" if skip_x else "?"

t = -1
while True:
inline = next(input, None)
if inline is None:
Expand All @@ -232,29 +240,50 @@ def aiw2yw(input, mapfile, output, skip_x):
if inline.startswith("#"):
continue

if not re.match(r'[01x]*$', ffline):
t += 1

if not re.match(r"[01x]*$", inline):
raise click.ClickException(f"{input_name}: unexpected data in AIGER witness file")

if len(inline) != aiger_map.input_count:
raise click.ClickException(
f"{input_name}: {mapfile.name}: number of inputs does not match, "
f"{len(inline)} in witness, {aiger_map.input_count} in map file")
f"{input_name}: {mapfile.name}: number of inputs does not match, "
f"{len(inline)} in witness, {aiger_map.input_count} in map file"
)

values = WitnessValues()
for i, v in enumerate(inline):
if outyw.t > 0 and i in aiger_map.init_inputs:
if v in skip or (t > 0 and i in aiger_map.init_inputs):
continue

try:
bit = aiger_map.sigmap.id_to_bit[i]
except IndexError:
bit = None
if bit is None:
missing.insert(i)
missing.add(i)
elif present_only:
seen.add(i)

values[bit] = v

outyw.step(values, skip_x=skip_x)
if present_only:
buffered_steps.append(values)
else:
outyw.step(values)

if present_only:
outyw = WriteWitness(output, "yosys-witness aiw2yw")

for clock in aiger_map.clocks:
outyw.add_clock(clock["path"], clock["offset"], clock["edge"])

for (path, offset), id in aiger_map.sigmap.bit_to_id.items():
if id in seen:
outyw.add_sig(path, offset, init_only=id in aiger_map.init_inputs)

for values in buffered_steps:
outyw.step(values)

outyw.end_trace()

Expand Down

0 comments on commit 94d7c22

Please sign in to comment.