Split sim models into multiple files and implement few

YosysHQ · May 10, 2024 · 1a7c18a · 1a7c18a
1 parent f70142c
commit 1a7c18a
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Showing 8 changed files with 84 additions and 83 deletions.
diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc
@@ -12,6 +12,9 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_m.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_u.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_l.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_m.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_u.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v))

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
@@ -28,12 +28,12 @@
 //endmodule
 
 // Bypass mode of NX_GCK_U
-(* blackbox *)
-module NX_BD(I, O);
-    input I;
-    output O;
-    parameter mode = "global_lowskew";
-endmodule
+//(* blackbox *)
+//module NX_BD(I, O);
+//    input I;
+//    output O;
+//    parameter mode = "global_lowskew";
+//endmodule
 
 //(* blackbox *)
 //module NX_DFF(I, CK, L, R, O);
@@ -51,12 +51,11 @@ endmodule
 //endmodule
 
 // Special mode of NX_DFF
-(* blackbox *)
-module NX_BFF(I, O);
-    input I;
-    output O;
-endmodule
-
+//(* blackbox *)
+//module NX_BFF(I, O);
+//    input I;
+//    output O;
+//endmodule
 
 (* blackbox *)
 module NX_DFR(I, CK, L, R, O);
@@ -79,17 +78,17 @@ module NX_DFR(I, CK, L, R, O);
 endmodule
 
 // Special mode of NX_DFR
-(* blackbox *)
-module NX_BFR(I, O);
-    input I;
-    output O;
-    parameter data_inv = 1'b0;
-    parameter iobname = "";
-    parameter location = "";
-    parameter mode = 0;
-    parameter path = 0;
-    parameter ring = 0;
-endmodule
+//(* blackbox *)
+//module NX_BFR(I, O);
+//    input I;
+//    output O;
+//    parameter data_inv = 1'b0;
+//    parameter iobname = "";
+//    parameter location = "";
+//    parameter mode = 0;
+//    parameter path = 0;
+//    parameter ring = 0;
+//endmodule
 
 (* blackbox *)
 module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13

diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v
@@ -1,14 +1,3 @@
-(* blackbox *)
-module NX_GCK_U(SI1, SI2, CMD, SO);
-    input CMD;
-    input SI1;
-    input SI2;
-    output SO;
-    parameter inv_in = 1'b0;
-    parameter inv_out = 1'b0;
-    parameter std_mode = "BYPASS";
-endmodule
-
 (* blackbox *)
 module NX_CDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BSRSTI, BDRSTI, BSRSTO
 , BDRSTO, BI1, BI2, BI3, BI4, BI5, BI6, BO1, BO2, BO3, BO4, BO5, BO6, CSRSTI, CDRSTI, CSRSTO, CDRSTO, CI1, CI2, CI3, CI4

diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v
@@ -52,54 +52,6 @@ assign { CO,  S4 } = A4 + B4 + CO3;
 
 endmodule
 
-(* abc9_box, lib_whitebox *)
-module NX_XRFB_64x18(input WCK, input [17:0] I, input [5:0] RA, WA, input WE, WEA, output [17:0] O);
-
-parameter wck_edge = 1'b0;
-parameter mem_ctxt = 1152'b0;
-
-reg [17:0] mem [63:0];
-
-integer i;
-initial begin
-	for (i = 0; i < 64; i = i + 1)
-		mem[i] = mem_ctxt[18*i +: 18];
-end
-
-wire clock = WCK ^ wck_edge;
-
-always @(posedge clock)
-	if (WE && WEA)
-		mem[WA] <= I;
-
-assign O = mem[RA];
-
-endmodule
-
-(* abc9_box, lib_whitebox *)
-module NX_XRFB_32x36(input WCK, input [35:0] I, input [4:0] RA, WA, input WE, WEA, output [35:0] O);
-
-parameter wck_edge = 1'b0;
-parameter mem_ctxt = 1152'b0;
-
-reg [35:0] mem [31:0];
-
-integer i;
-initial begin
-	for (i = 0; i < 32; i = i + 1)
-		mem[i] = mem_ctxt[36*i +: 36];
-end
-
-wire clock = WCK ^ wck_edge;
-
-always @(posedge clock)
-	if (WE && WEA)
-		mem[WA] <= I;
-
-assign O = mem[RA];
-
-endmodule
-
 module NX_IOB(I, C, T, O, IO);
     input C;
     input I;
@@ -205,3 +157,31 @@ module NX_CY_1BIT(CI, A, B, S, CO);
 
     assign {CO, S} = A + B + CI;
 endmodule
+
+module NX_BD(I, O);
+    input I;
+    output O;
+    parameter mode = "global_lowskew";
+
+    assign O = I;
+endmodule
+
+module NX_BFF(I, O);
+    input I;
+    output O;
+
+    assign O = I;
+endmodule
+
+module NX_BFR(I, O);
+    input I;
+    output O;
+    parameter data_inv = 1'b0;
+    parameter iobname = "";
+    parameter location = "";
+    parameter mode = 0;
+    parameter path = 0;
+    parameter ring = 0;
+
+    assign O = data_inv ? ~I : I;
+endmodule
diff --git a/techlibs/nanoxplore/cells_sim_l.v b/techlibs/nanoxplore/cells_sim_l.v
diff --git a/techlibs/nanoxplore/cells_sim_m.v b/techlibs/nanoxplore/cells_sim_m.v
diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v
@@ -0,0 +1,30 @@
+module NX_GCK_U(SI1, SI2, CMD, SO);
+    input CMD;
+    input SI1;
+    input SI2;
+    output SO;
+    parameter inv_in = 1'b0;
+    parameter inv_out = 1'b0;
+    parameter std_mode = "BYPASS";
+
+    wire SI1_int = inv_in ? ~SI1 : SI1;
+    wire SI2_int = inv_in ? ~SI2 : SI2;
+
+    wire SO_int;
+    generate if (std_mode == "BYPASS") begin
+        assign SO_int = SI1_int;
+    end
+    else if (std_mode == "MUX") begin
+        assign SO_int = CMD ? SI1_int : SI2_int;
+    end
+    else if (std_mode == "CKS") begin
+        assign SO_int = CMD ? SI1_int : 1'b0;
+    end
+    else if (std_mode == "CSC") begin
+        assign SO_int = CMD;
+    end
+    else
+    $error("Unrecognised std_mode");
+    endgenerate
+    assign SO = inv_out ? ~SO_int : SO_int;
+endmodule
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -229,7 +229,7 @@ struct SynthNanoXplorePass : public ScriptPass
 
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v");
+			run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim" + postfix + ".v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v");
 			run("techmap -map +/nanoxplore/cells_wrap.v");
 			run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));