RMSC with operating frequency of 300MHz. Coded, simulated and synthesized on Verilog RTL 72 stages Pipelining of division and square root block producing the result using a synchronous FIFO. Tools and Languages: Synopsys VCS, Synopsys Design Vision, GTK Wave, NC-Verilog, Verilog HDL
forked from ameyjain/VERILOG-RootMeanSquareCalculator
-
Notifications
You must be signed in to change notification settings - Fork 0
RMSC with operating frequency of 300MHz. Coded, simulated and synthesized on Verilog RTL 72 stages Pipelining of division and square root block producing the result using a synchronous FIFO. Tools and Languages: Synopsys VCS, Synopsys Design Vision, GTK Wave, NC-Verilog, Verilog HDL
PMLSTaisen/VERILOG-RootMeanSquareCalculator
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
RMSC with operating frequency of 300MHz. Coded, simulated and synthesized on Verilog RTL 72 stages Pipelining of division and square root block producing the result using a synchronous FIFO. Tools and Languages: Synopsys VCS, Synopsys Design Vision, GTK Wave, NC-Verilog, Verilog HDL
Resources
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published
Languages
- Verilog 76.8%
- Pascal 23.2%