RMSC with operating frequency of 300MHz. Coded, simulated and synthesized on Verilog RTL 72 stages Pipelining of division and square root block producing the result using a synchronous FIFO. Tools and Languages: Synopsys VCS, Synopsys Design Vision, GTK Wave, NC-Verilog, Verilog HDL
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RMSC with operating frequency of 300MHz. Coded, simulated and synthesized on Verilog RTL 72 stages Pipelining of division and square root block producing the result using a synchronous FIFO. Tools and Languages: Synopsys VCS, Synopsys Design Vision, GTK Wave, NC-Verilog, Verilog HDL
ameyjain/VERILOG-RootMeanSquareCalculator
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RMSC with operating frequency of 300MHz. Coded, simulated and synthesized on Verilog RTL 72 stages Pipelining of division and square root block producing the result using a synchronous FIFO. Tools and Languages: Synopsys VCS, Synopsys Design Vision, GTK Wave, NC-Verilog, Verilog HDL
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