Added full_case and parallel_case attributes (#274)

CHANGELOG.md

@@ -7,6 +7,8 @@
 
 ### New Features
 
+* `unique`, `unique0`, and `priority` case statements now produce corresponding
+  `parallel_case` and `full_case` statement attributes
 * Added support for attributes in unary, binary, and ternary expressions
 * Added support for shadowing interface names with local typenames
 * Added support for streaming concatenations within ternary expressions

src/Convert/Unique.hs

@@ -3,9 +3,9 @@
  -
  - Conversion for `unique`, `unique0`, and `priority` (verification checks)
  -
- - This conversion simply drops these keywords, as they are only used for
- - optimization and verification. There may be ways to communicate these
- - attributes to certain downstream toolchains.
+ - For `case`, these verification checks are replaced with equivalent
+ - `full_case` and `parallel_case` attributes. For `if`, they are simply
+ - dropped.
  -}
 
 module Convert.Unique (convert) where
@@ -21,6 +21,19 @@ convert =
 convertStmt :: Stmt -> Stmt
 convertStmt (If _ cc s1 s2) =
     If NoCheck cc s1 s2
-convertStmt (Case _ kw expr cases) =
-    Case NoCheck kw expr cases
+convertStmt (Case Priority kw expr cases) =
+    StmtAttr caseAttr caseStmt
+    where
+        caseAttr = Attr [("full_case", Nil)]
+        caseStmt = Case NoCheck kw expr cases
+convertStmt (Case Unique kw expr cases) =
+    StmtAttr caseAttr caseStmt
+    where
+        caseAttr = Attr [("full_case", Nil), ("parallel_case", Nil)]
+        caseStmt = Case NoCheck kw expr cases
+convertStmt (Case Unique0 kw expr cases) =
+    StmtAttr caseAttr caseStmt
+    where
+        caseAttr = Attr [("parallel_case", Nil)]
+        caseStmt = Case NoCheck kw expr cases
 convertStmt other = other

test/core/case_violation_checks.sv

@@ -0,0 +1,41 @@
+module UniqueCase(
+    input logic [1:0] select,
+    output logic [3:0] data
+);
+    always_comb begin
+        data = 4'b0;
+        unique case (select)
+            2'd0: data = 4'ha;
+            2'd1: data = 4'h6;
+            2'd2: data = 4'h3;
+        endcase
+    end
+endmodule
+
+module Unique0Case(
+    input logic [1:0] select,
+    output logic [3:0] data
+);
+    always_comb begin
+        data = 4'b0;
+        unique0 case (select)
+            2'd0: data = 4'ha;
+            2'd1: data = 4'h6;
+            2'd2: data = 4'h3;
+        endcase
+    end
+endmodule
+
+module PriorityCase(
+    input logic [1:0] select,
+    output logic [3:0] data
+);
+    always_comb begin
+        data = 4'b0;
+        priority case (select)
+            2'd0: data = 4'ha;
+            2'd1: data = 4'h6;
+            2'd2: data = 4'h3;
+        endcase
+    end
+endmodule

test/core/case_violation_checks.sv.pat

@@ -0,0 +1,3 @@
+affirm (* full_case, parallel_case *)
+affirm (* parallel_case *)
+affirm (* full_case *)

test/core/case_violation_checks.v

@@ -0,0 +1,41 @@
+module UniqueCase(
+    input wire [1:0] select,
+    output reg [3:0] data
+);
+    always @* begin
+        data = 4'b0;
+        case (select)
+            2'd0: data = 4'ha;
+            2'd1: data = 4'h6;
+            2'd2: data = 4'h3;
+        endcase
+    end
+endmodule
+
+module Unique0Case(
+    input wire [1:0] select,
+    output reg [3:0] data
+);
+    always @* begin
+        data = 4'b0;
+        case (select)
+            2'd0: data = 4'ha;
+            2'd1: data = 4'h6;
+            2'd2: data = 4'h3;
+        endcase
+    end
+endmodule
+
+module PriorityCase(
+    input wire [1:0] select,
+    output reg [3:0] data
+);
+    always @* begin
+        data = 4'b0;
+        case (select)
+            2'd0: data = 4'ha;
+            2'd1: data = 4'h6;
+            2'd2: data = 4'h3;
+        endcase
+    end
+endmodule

test/core/case_violation_checks_tb.v

@@ -0,0 +1,7 @@
+module top;
+    reg [1:0] select;
+    wire [3:0] data [2:0];
+    UniqueCase case0(select, data[0]);
+    Unique0Case case1(select, data[1]);
+    PriorityCase case2(select, data[2]);
+endmodule