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yourcomrade committed Jul 10, 2024
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2 changes: 2 additions & 0 deletions .qsys_edit/filters.xml
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<?xml version="1.0" encoding="UTF-8"?>
<filters version="23.1" />
Empty file added .qsys_edit/mandebrot_plot_schematic.nlv
Empty file.
12 changes: 12 additions & 0 deletions .qsys_edit/preferences.xml
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<?xml version="1.0" encoding="UTF-8"?>
<preferences>
<debug showDebugMenu="0" />
<systemtable filter="All Interfaces">
<columns>
<connections preferredWidth="111" />
<irq preferredWidth="34" />
</columns>
</systemtable>
<library expandedCategories="Library,Project" />
<window width="1938" height="1038" x="-9" y="-9" />
</preferences>
75 changes: 75 additions & 0 deletions I2C_Controller.v
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// --------------------------------------------------------------------
// Copyright (c) 2005 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altrea Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// --------------------------------------------------------------------
//
// Major Functions:i2c controller
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Joe Yang :| 05/07/10 :| Initial Revision
// V2.0 :| Joe Yang :| 12/12/16 :| Initial Revision
// --------------------------------------------------------------------
module I2C_Controller (
input CLOCK,
input [23:0]I2C_DATA,
input GO,
input RESET,
input W_R,
inout I2C_SDAT,
output I2C_SCLK,
output END,
output ACK
);

wire SDAO ;

assign I2C_SDAT = SDAO?1'bz :0 ;

I2C_WRITE_WDATA wrd(
.RESET_N ( RESET),
.PT_CK ( CLOCK),
.GO ( GO ),
.END_OK ( END ),
.ACK_OK ( ACK ),
.BYTE_NUM ( 2 ), //2byte
.SDAI ( I2C_SDAT ),//IN
.SDAO ( SDAO ),//OUT
.SCLO ( I2C_SCLK ),
.SLAVE_ADDRESS( I2C_DATA[23:16] ),
.REG_DATA ( I2C_DATA[15:0] )
);



endmodule
158 changes: 158 additions & 0 deletions I2C_HDMI_Config.v
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module I2C_HDMI_Config ( // Host Side
iCLK,
iRST_N,
// I2C Side
I2C_SCLK,
I2C_SDAT,
HDMI_TX_INT,
READY
);
// Host Side
input iCLK;
input iRST_N;
// I2C Side
output I2C_SCLK;
inout I2C_SDAT;
input HDMI_TX_INT;
output READY ;

// Internal Registers/Wires
reg [15:0] mI2C_CLK_DIV;
reg [23:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
reg [15:0] LUT_DATA;
reg [5:0] LUT_INDEX;
reg [3:0] mSetup_ST;
reg READY ;

// Clock Setting
parameter CLK_Freq = 50000000; // 50 MHz
parameter I2C_Freq = 20000; // 20 KHz
// LUT Data Number
parameter LUT_SIZE = 31;

///////////////////// I2C Control Clock ////////////////////////
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
mI2C_CTRL_CLK <= 0;
mI2C_CLK_DIV <= 0;
end
else
begin
if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
mI2C_CLK_DIV <= mI2C_CLK_DIV+1;
else
begin
mI2C_CLK_DIV <= 0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
////////////////////////////////////////////////////////////////////
I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(I2C_SCLK), // I2C CLOCK
.I2C_SDAT(I2C_SDAT), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(iRST_N) );
////////////////////////////////////////////////////////////////////
////////////////////// Config Control ////////////////////////////
always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
begin
if(!iRST_N)
begin
READY<=0;
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
end
else
begin
if(LUT_INDEX<LUT_SIZE)
begin
READY<=0;
case(mSetup_ST)
0: begin
mI2C_DATA <= {8'h72,LUT_DATA};
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: begin
if(mI2C_END)
begin
if(!mI2C_ACK)
mSetup_ST <= 2;
else
mSetup_ST <= 0;
mI2C_GO <= 0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX+1;
mSetup_ST <= 0;
end
endcase
end
else
begin
READY<=1;
if(!HDMI_TX_INT)
begin
LUT_INDEX <= 0;
end
else
LUT_INDEX <= LUT_INDEX;
end
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
always
begin
case(LUT_INDEX)

// Video Config Data
0 : LUT_DATA <= 16'h9803; //Must be set to 0x03 for proper operation
1 : LUT_DATA <= 16'h0100; //Set 'N' value at 6144
2 : LUT_DATA <= 16'h0218; //Set 'N' value at 6144
3 : LUT_DATA <= 16'h0300; //Set 'N' value at 6144
4 : LUT_DATA <= 16'h1470; // Set Ch count in the channel status to 8.
5 : LUT_DATA <= 16'h1520; //Input 444 (RGB or YCrCb) with Separate Syncs, 48kHz fs
6 : LUT_DATA <= 16'h1630; //Output format 444, 24-bit input
7 : LUT_DATA <= 16'h1846; //Disable CSC
8 : LUT_DATA <= 16'h4080; //General control packet enable
9 : LUT_DATA <= 16'h4110; //Power down control
10 : LUT_DATA <= 16'h49A8; //Set dither mode - 12-to-10 bit
11 : LUT_DATA <= 16'h5510; //Set RGB in AVI infoframe
12 : LUT_DATA <= 16'h5608; //Set active format aspect
13 : LUT_DATA <= 16'h96F6; //Set interrup
14 : LUT_DATA <= 16'h7307; //Info frame Ch count to 8
15 : LUT_DATA <= 16'h761f; //Set speaker allocation for 8 channels
16 : LUT_DATA <= 16'h9803; //Must be set to 0x03 for proper operation
17 : LUT_DATA <= 16'h9902; //Must be set to Default Value
18 : LUT_DATA <= 16'h9ae0; //Must be set to 0b1110000
19 : LUT_DATA <= 16'h9c30; //PLL filter R1 value
20 : LUT_DATA <= 16'h9d61; //Set clock divide
21 : LUT_DATA <= 16'ha2a4; //Must be set to 0xA4 for proper operation
22 : LUT_DATA <= 16'ha3a4; //Must be set to 0xA4 for proper operation
23 : LUT_DATA <= 16'ha504; //Must be set to Default Value
24 : LUT_DATA <= 16'hab40; //Must be set to Default Value
25 : LUT_DATA <= 16'haf16; //Select HDMI mode
26 : LUT_DATA <= 16'hba60; //No clock delay
27 : LUT_DATA <= 16'hd1ff; //Must be set to Default Value
28 : LUT_DATA <= 16'hde10; //Must be set to Default for proper operation
29 : LUT_DATA <= 16'he460; //Must be set to Default Value
30 : LUT_DATA <= 16'hfa7d; //Nbr of times to look for good phase

default: LUT_DATA <= 16'h9803;
endcase
end
////////////////////////////////////////////////////////////////////
endmodule
106 changes: 106 additions & 0 deletions I2C_WRITE_WDATA.v
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module I2C_WRITE_WDATA (
input RESET_N ,
input PT_CK,
input GO,
input [15:0] REG_DATA,
input [7:0] SLAVE_ADDRESS,
input SDAI,
output reg SDAO,
output reg SCLO,
output reg END_OK,

//--for test
output reg [7:0] ST ,
output reg [7:0] CNT,
output reg [7:0] BYTE,
output reg ACK_OK,
input [7:0] BYTE_NUM // 4 : 4 byte
);

//===reg/wire
reg [8:0]A ;
reg [7:0]DELY ;

always @( negedge RESET_N or posedge PT_CK )begin
if (!RESET_N ) ST <=0;
else
case (ST)
0: begin //start
SDAO <=1;
SCLO <=1;
ACK_OK <=0;
CNT <=0;
END_OK <=1;
BYTE <=0;
if (GO) ST <=30 ; // inital
end
1: begin //start
ST <=2 ;
{ SDAO, SCLO } <= 2'b01;
A <= {SLAVE_ADDRESS ,1'b1 };//WRITE COMMAND
end
2: begin //start
ST <=3 ;
{ SDAO, SCLO } <= 2'b00;
end

3: begin
ST <=4 ;
{ SDAO, A } <= { A ,1'b0 };
end
4: begin
ST <=5 ;
SCLO <= 1'b1 ;
CNT <= CNT +1 ;
end

5: begin
SCLO <= 1'b0 ;
if (CNT==9) begin
if ( BYTE == BYTE_NUM ) ST <= 6 ;
else begin
CNT <=0 ;
ST <= 2 ;
if ( BYTE ==0 ) begin BYTE <=1 ; A <= {REG_DATA[15:8] ,1'b1 }; end
else if ( BYTE ==1 ) begin BYTE <=2 ; A <= {REG_DATA[7:0] ,1'b1 }; end
end
if (SDAI ) ACK_OK <=1 ;
end
else ST <= 2;
end

6: begin //stop
ST <=7 ;
{ SDAO, SCLO } <= 2'b00;
end

7: begin //stop
ST <=8 ;
{ SDAO, SCLO } <= 2'b01;
end
8: begin //stop
ST <=9 ;
{ SDAO, SCLO } <= 2'b11;

end
9: begin
ST <= 30;
SDAO <=1;
SCLO <=1;
CNT <=0;
END_OK <=1;
BYTE <=0;
end
//--- END ---
30: begin
if (!GO) ST <=31;
end
31: begin //
END_OK<=0;
ACK_OK<=0;
ST <=1;
end
endcase
end

endmodule
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