Blackbox SDF timing fixes

[acomodi]

Description

Summary of changes:

1. Traverse through input and output pins of blackbox primitives and populate timing_arcs, Tsu, Thld, Tco in local netist_writer data structure.

2. Store and output the correct reference clock ports in SDF writing.

Related Issue

SymbiFlow#537

Motivation and Context

There are multiple issues related to SDF writer for Blackbox primitive

1. The primitives being modelled as Blackbox have combinational and sequential timings. In present --analysis code, BlackBox combinational and sequential timings are not getting populated

2. Blackbox could have more than 1 reference clocks (e.g. Dual Port RAM). Current SDF generation does not handle timing checks w.r.t. specific clock. It uses a generic name "clk" to write out timing checks

How Has This Been Tested?

• Turned on analysis option and generated the SDF for following test suite
  https://github.com/QuickLogic-Corp/symbiflow-arch-defs/tree/quicklogic-upstream-rebase/quicklogic/pp3/tests

• ran the vtr_reg_strong and passed.

Types of changes

• Bug fix (change which fixes an issue)
• New feature (change which adds functionality)
• Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

• My change requires a change to the documentation
• I have updated the documentation accordingly
• I have added tests to cover my changes
• All new and existing tests passed

[acomodi]

@tpagarani FYI

[acomodi]

@vaughnbetz FYI

[vaughnbetz]

Looks good; just have some suggestions for additional comments on data structures and types.

[vaughnbetz]

Looks good to me. Go ahead and merge when CI finishes (or I will, but you can probably get it in faster if you merge yourself).

[vaughnbetz]

Thanks, LGTM.