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Fix inconsistent reset style
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@ultraembedded
ultraembedded committed Sep 2, 2019
1 parent 5f749d8 commit 0958c84
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Showing 13 changed files with 136 additions and 146 deletions.
38 changes: 19 additions & 19 deletions README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -48,16 +48,16 @@ Design Summary:
Number of errors: 0
Number of warnings: 10
Slice Logic Utilization:
Number of Slice Registers: 2,670 out of 11,440 23%
Number used as Flip Flops: 2,670
Number of Slice Registers: 2,681 out of 11,440 23%
Number used as Flip Flops: 2,681
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,694 out of 5,720 99%
Number used as logic: 5,142 out of 5,720 89%
Number using O6 output only: 3,958
Number using O5 output only: 261
Number using O5 and O6: 923
Number of Slice LUTs: 5,652 out of 5,720 98%
Number used as logic: 5,072 out of 5,720 88%
Number using O6 output only: 3,889
Number using O5 output only: 279
Number using O5 and O6: 904
Number used as ROM: 0
Number used as Memory: 519 out of 1,440 36%
Number used as Dual Port RAM: 518
Expand All @@ -69,21 +69,21 @@ Slice Logic Utilization:
Number using O6 output only: 1
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 33
Number with same-slice register load: 21
Number with same-slice carry load: 12
Number used exclusively as route-thrus: 61
Number with same-slice register load: 47
Number with same-slice carry load: 14
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,430 out of 1,430 100%
Number of MUXCYs used: 1,288 out of 2,860 45%
Number of LUT Flip Flop pairs used: 5,710
Number with an unused Flip Flop: 3,194 out of 5,710 55%
Number with an unused LUT: 16 out of 5,710 1%
Number of fully used LUT-FF pairs: 2,500 out of 5,710 43%
Number of unique control sets: 216
Number of MUXCYs used: 1,300 out of 2,860 45%
Number of LUT Flip Flop pairs used: 5,701
Number with an unused Flip Flop: 3,190 out of 5,701 55%
Number with an unused LUT: 49 out of 5,701 1%
Number of fully used LUT-FF pairs: 2,462 out of 5,701 43%
Number of unique control sets: 215
Number of slice register sites lost
to control set restrictions: 881 out of 11,440 7%
to control set restrictions: 854 out of 11,440 7%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
Expand All @@ -92,8 +92,8 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 147 out of 186 79%
Number of LOCed IOBs: 147 out of 147 100%
Number of bonded IOBs: 61 out of 186 32%
Number of LOCed IOBs: 61 out of 61 100%
IOB Flip Flops: 61
Specific Feature Utilization:
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Binary file modified bitstreams/fpga_xc9.bit
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36 changes: 18 additions & 18 deletions src_v/audio/audio.v
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Original file line number Diff line number Diff line change
Expand Up @@ -71,7 +71,7 @@ module audio
//-----------------------------------------------------------------
reg [31:0] wr_data_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
wr_data_q <= 32'b0;
else
Expand All @@ -96,7 +96,7 @@ assign cfg_wready_o = cfg_awready_o;
//-----------------------------------------------------------------
reg audio_cfg_wr_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
audio_cfg_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
Expand All @@ -107,7 +107,7 @@ else
// audio_cfg_int_threshold [internal]
reg [15:0] audio_cfg_int_threshold_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
audio_cfg_int_threshold_q <= 16'd`AUDIO_CFG_INT_THRESHOLD_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
Expand All @@ -119,7 +119,7 @@ wire [15:0] audio_cfg_int_threshold_out_w = audio_cfg_int_threshold_q;
// audio_cfg_byte_swap [internal]
reg audio_cfg_byte_swap_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
audio_cfg_byte_swap_q <= 1'd`AUDIO_CFG_BYTE_SWAP_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
Expand All @@ -131,7 +131,7 @@ wire audio_cfg_byte_swap_out_w = audio_cfg_byte_swap_q;
// audio_cfg_ch_swap [internal]
reg audio_cfg_ch_swap_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
audio_cfg_ch_swap_q <= 1'd`AUDIO_CFG_CH_SWAP_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
Expand All @@ -143,7 +143,7 @@ wire audio_cfg_ch_swap_out_w = audio_cfg_ch_swap_q;
// audio_cfg_target [internal]
reg [1:0] audio_cfg_target_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
audio_cfg_target_q <= 2'd`AUDIO_CFG_TARGET_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
Expand All @@ -155,7 +155,7 @@ wire [1:0] audio_cfg_target_out_w = audio_cfg_target_q;
// audio_cfg_vol_ctrl [internal]
reg [2:0] audio_cfg_vol_ctrl_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
audio_cfg_vol_ctrl_q <= 3'd`AUDIO_CFG_VOL_CTRL_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
Expand All @@ -167,7 +167,7 @@ wire [2:0] audio_cfg_vol_ctrl_out_w = audio_cfg_vol_ctrl_q;
// audio_cfg_buffer_rst [auto_clr]
reg audio_cfg_buffer_rst_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
audio_cfg_buffer_rst_q <= 1'd`AUDIO_CFG_BUFFER_RST_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CFG))
Expand All @@ -183,7 +183,7 @@ wire audio_cfg_buffer_rst_out_w = audio_cfg_buffer_rst_q;
//-----------------------------------------------------------------
reg audio_status_wr_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
audio_status_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_STATUS))
Expand All @@ -199,7 +199,7 @@ else
//-----------------------------------------------------------------
reg audio_clk_div_wr_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
audio_clk_div_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_DIV))
Expand All @@ -210,7 +210,7 @@ else
// audio_clk_div_whole_cycles [internal]
reg [15:0] audio_clk_div_whole_cycles_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
audio_clk_div_whole_cycles_q <= 16'd`AUDIO_CLK_DIV_WHOLE_CYCLES_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_DIV))
Expand All @@ -224,7 +224,7 @@ wire [15:0] audio_clk_div_whole_cycles_out_w = audio_clk_div_whole_cycles_q;
//-----------------------------------------------------------------
reg audio_clk_frac_wr_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
audio_clk_frac_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_FRAC))
Expand All @@ -235,7 +235,7 @@ else
// audio_clk_frac_numerator [internal]
reg [15:0] audio_clk_frac_numerator_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
audio_clk_frac_numerator_q <= 16'd`AUDIO_CLK_FRAC_NUMERATOR_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_FRAC))
Expand All @@ -247,7 +247,7 @@ wire [15:0] audio_clk_frac_numerator_out_w = audio_clk_frac_numerator_q;
// audio_clk_frac_denominator [internal]
reg [15:0] audio_clk_frac_denominator_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
audio_clk_frac_denominator_q <= 16'd`AUDIO_CLK_FRAC_DENOMINATOR_DEFAULT;
else if (write_en_w && (cfg_awaddr_i[7:0] == `AUDIO_CLK_FRAC))
Expand All @@ -261,7 +261,7 @@ wire [15:0] audio_clk_frac_denominator_out_w = audio_clk_frac_denominator_q;
//-----------------------------------------------------------------
reg audio_fifo_write_wr_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
audio_fifo_write_wr_q <= 1'b0;
else if (write_en_w && (cfg_awaddr_i[7:0] >= `AUDIO_FIFO_WRITE && cfg_awaddr_i[7:0] < (`AUDIO_FIFO_WRITE + 8'd32)))
Expand Down Expand Up @@ -326,7 +326,7 @@ end
//-----------------------------------------------------------------
reg rvalid_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
rvalid_q <= 1'b0;
else if (read_en_w)
Expand All @@ -341,7 +341,7 @@ assign cfg_rvalid_o = rvalid_q;
//-----------------------------------------------------------------
reg [31:0] rd_data_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
rd_data_q <= 32'b0;
else if (!cfg_rvalid_o || cfg_rready_i)
Expand All @@ -355,7 +355,7 @@ assign cfg_rresp_o = 2'b0;
//-----------------------------------------------------------------
reg bvalid_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
bvalid_q <= 1'b0;
else if (write_en_w)
Expand Down
12 changes: 1 addition & 11 deletions src_v/audio/audio_dac.v
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Original file line number Diff line number Diff line change
Expand Up @@ -52,16 +52,6 @@ module audio_dac



//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
localparam CLK_RATE_KHZ = 50000;
localparam AUDIO_RATE = 44100;

// Generated params
localparam WHOLE_CYCLES = (CLK_RATE_KHZ*1000) / (AUDIO_RATE*128);
localparam ERROR_BASE = 10000;
localparam [63:0] ERRORS_PER_BIT = ((CLK_RATE_KHZ * 1000 * ERROR_BASE) / (AUDIO_RATE*128)) - (WHOLE_CYCLES * ERROR_BASE);

//-----------------------------------------------------------------
// External clock source
Expand All @@ -77,7 +67,7 @@ reg [15:0] left_q;
reg [15:0] right_q;
reg pop_q;

always @ (posedge rst_i or posedge clk_i )
always @ (posedge clk_i )
begin
if (rst_i)
begin
Expand Down
8 changes: 4 additions & 4 deletions src_v/audio/audio_fifo.v
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Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,7 @@ wire [10:0] write_next_w = wr_ptr_q + 11'd1;

wire full_w = (write_next_w == rd_ptr_q);

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
wr_ptr_q <= 11'b0;
else if (flush_i)
Expand All @@ -78,15 +78,15 @@ else if (push_i & !full_w)
wire read_ok_w = (wr_ptr_q != rd_ptr_q);
reg rd_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
rd_q <= 1'b0;
else if (flush_i)
rd_q <= 1'b0;
else
rd_q <= read_ok_w;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
rd_ptr_q <= 11'b0;
else if (flush_i)
Expand All @@ -101,7 +101,7 @@ else if (read_ok_w && ((!valid_o) || (valid_o && pop_i)))
reg rd_skid_q;
reg [31:0] rd_skid_data_q;

always @ (posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
if (rst_i)
begin
rd_skid_q <= 1'b0;
Expand Down
2 changes: 1 addition & 1 deletion src_v/audio/sigma_dac.v
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Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,7 @@ always @ *
always @ *
sigma_adder_r = delta_adder_r + sigma_latch_q;

always @(posedge clk_i or posedge rst_i)
always @ (posedge clk_i )
begin
if (rst_i)
begin
Expand Down
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