update logphy

ucb-ucie · May 3, 2024 · aea5de3 · aea5de3
1 parent 1a31e02
commit aea5de3
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Showing 3 changed files with 46 additions and 5 deletions.
diff --git a/src/main/scala/logphy/LinkTrainingFSM.scala b/src/main/scala/logphy/LinkTrainingFSM.scala
@@ -118,9 +118,32 @@ class LinkTrainingFSM(
   rdiBringup.io.rdiIO <> io.rdi.rdiBringupIO
   rdiBringup.io.sbTrainIO.msgReq.nodeq()
   rdiBringup.io.sbTrainIO.msgReqStatus.noenq()
+  val plStateStatus = WireInit(rdiBringup.io.rdiIO.plStateStatus)
 
   // TODO: incorporate lpstatereq
-  currentState := nextState
+  currentState := PriorityMux(
+    Seq(
+      (rdiBringup.io.rdiIO.plStateStatus === PhyState.reset, nextState),
+      (
+        rdiBringup.io.rdiIO.plStateStatus === PhyState.active,
+        LinkTrainingState.active,
+      ),
+      (
+        rdiBringup.io.rdiIO.plStateStatus === PhyState.retrain,
+        LinkTrainingState.retrain,
+      ),
+      (
+        rdiBringup.io.rdiIO.plStateStatus === PhyState.linkError,
+        LinkTrainingState.linkError,
+      ),
+    ),
+  )
+  // currentState := Mux(
+  //   plStateStatus === PhyState.reset,
+  //   nextState,
+  /* Mux(plStateStatus === PhyState.linkError, LinkTrainingState.linkError,
+   * Mux(plStateStatus === )), */
+  // )
   io.sidebandFSMIO.rxMode := Mux(
     currentState === LinkTrainingState.sbInit &&
       (sbInitSubState === SBInitSubState.SEND_CLOCK ||
@@ -150,6 +173,9 @@ class LinkTrainingFSM(
 
   rdiBringup.io.internalError := currentState === LinkTrainingState.linkError
 
+  /** TODO: need to set accurately */
+  rdiBringup.io.internalRetrain := false.B
+
   private object ActiveSubState extends ChiselEnum {
     val IDLE = Value
   }

diff --git a/src/main/scala/logphy/LogPhyTypes.scala b/src/main/scala/logphy/LogPhyTypes.scala
@@ -7,7 +7,7 @@ import sideband.SidebandParams
 import interfaces._
 
 object LinkTrainingState extends ChiselEnum {
-  val reset, sbInit, mbInit, linkInit, active, linkError = Value
+  val reset, sbInit, mbInit, linkInit, active, linkError, retrain = Value
 }
 
 object MsgSource extends ChiselEnum {

diff --git a/src/main/scala/logphy/RdiBringup.scala b/src/main/scala/logphy/RdiBringup.scala
@@ -32,6 +32,7 @@ class RdiBringup extends Module {
     val sbTrainIO = Flipped(new SBMsgWrapperTrainIO)
     val active = Output(Bool())
     val internalError = Input(Bool())
+    val internalRetrain = Input(Bool())
   })
 
   io.rdiIO.plClkReq := true.B
@@ -53,8 +54,10 @@ class RdiBringup extends Module {
   io.sbTrainIO.msgReq.noenq()
   io.sbTrainIO.msgReqStatus.nodeq()
   state := nextState
-  when(io.internalError) {
-    state := PhyState.linkError
+  when(io.internalError || io.rdiIO.lpLinkError) {
+    nextState := PhyState.linkError
+  }.elsewhen(io.internalRetrain) {
+    nextState := PhyState.retrain
   }
 
   private val resetSubstate = RegInit(ResetSubState.WAIT_LP_STATE_REQ)
@@ -68,12 +71,24 @@ class RdiBringup extends Module {
   }
 
   io.rdiIO.plStallReq := stallReqAckState === StallReqAckState.LP_STALLACK_WAIT
+  private val prevReq = RegInit(PhyStateReq.nop)
+  prevReq := io.rdiIO.lpStateReq
+
+  /** TODO: Implement Table 8-3 from spec */
+  when(io.rdiIO.lpStateReq =/= PhyStateReq.nop) {
+    when(state =/= PhyState.reset || prevReq === PhyStateReq.nop) {
+      nextState := io.rdiIO.lpStateReq.asUInt.asTypeOf(PhyState())
+    }
+  }
 
   switch(state) {
     is(PhyState.reset) {
       switch(resetSubstate) {
         is(ResetSubState.WAIT_LP_STATE_REQ) {
-          when(io.rdiIO.lpStateReq === PhyStateReq.active) {
+          when(
+            nextState === PhyState.active,
+          ) {
+            state := PhyState.reset
             resetSubstate := ResetSubState.REQ_ACTIVE_SEND
           }
         }