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change adc driver not to use chibios hal
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,107 @@ | ||
#include "ch.h" | ||
#include "hal.h" | ||
#include "nanovna.h" | ||
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#define ADC_TR(low, high) (((uint32_t)(high) << 16U) | \ | ||
(uint32_t)(low)) | ||
#define ADC_SMPR_SMP_1P5 0U /**< @brief 14 cycles conversion time */ | ||
#define ADC_CFGR1_RES_12BIT (0U << 3U) | ||
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void adc_init(void) | ||
{ | ||
rccEnableADC1(FALSE); | ||
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/* Calibration procedure.*/ | ||
ADC->CCR = 0; | ||
ADC1->CR |= ADC_CR_ADCAL; | ||
while (ADC1->CR & ADC_CR_ADCAL) | ||
; | ||
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ADC1->CR = ADC_CR_ADEN; | ||
while (!(ADC1->ISR & ADC_ISR_ADRDY)) | ||
; | ||
} | ||
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uint16_t adc_single_read(ADC_TypeDef *adc, uint32_t chsel) | ||
{ | ||
/* ADC setup */ | ||
adc->ISR = adc->ISR; | ||
adc->IER = 0; | ||
adc->TR = ADC_TR(0, 0); | ||
adc->SMPR = ADC_SMPR_SMP_1P5; | ||
adc->CFGR1 = ADC_CFGR1_RES_12BIT; | ||
adc->CHSELR = chsel; | ||
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/* ADC conversion start.*/ | ||
adc->CR |= ADC_CR_ADSTART; | ||
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while (adc->CR & ADC_CR_ADSTART) | ||
; | ||
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return adc->DR; | ||
} | ||
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void adc_start_analog_watchdogd(ADC_TypeDef *adc, uint32_t chsel) | ||
{ | ||
uint32_t cfgr1; | ||
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cfgr1 = ADC_CFGR1_RES_12BIT | ADC_CFGR1_AWDEN | ||
| ADC_CFGR1_EXTEN_0 // rising edge of external trigger | ||
| ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1; // TRG3 , /* CFGR1 */ | ||
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/* ADC setup, if it is defined a callback for the analog watch dog then it | ||
is enabled.*/ | ||
adc->ISR = adc->ISR; | ||
adc->IER = ADC_IER_AWDIE; | ||
adc->TR = ADC_TR(0, 2000); | ||
adc->SMPR = ADC_SMPR_SMP_1P5; | ||
adc->CHSELR = chsel; | ||
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/* ADC configuration and start.*/ | ||
adc->CFGR1 = cfgr1; | ||
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/* ADC conversion start.*/ | ||
adc->CR |= ADC_CR_ADSTART; | ||
} | ||
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void adc_stop(ADC_TypeDef *adc) | ||
{ | ||
if (adc->CR & ADC_CR_ADEN) { | ||
if (adc->CR & ADC_CR_ADSTART) { | ||
adc->CR |= ADC_CR_ADSTP; | ||
while (adc->CR & ADC_CR_ADSTP) | ||
; | ||
} | ||
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/* adc->CR |= ADC_CR_ADDIS; | ||
while (adc->CR & ADC_CR_ADDIS) | ||
;*/ | ||
} | ||
} | ||
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void adc_interrupt(ADC_TypeDef *adc) | ||
{ | ||
uint32_t isr = adc->ISR; | ||
adc->ISR = isr; | ||
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if (isr & ADC_ISR_OVR) { | ||
/* ADC overflow condition, this could happen only if the DMA is unable | ||
to read data fast enough.*/ | ||
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} | ||
if (isr & ADC_ISR_AWD) { | ||
/* Analog watchdog error.*/ | ||
extern int awd_count; | ||
awd_count++; | ||
} | ||
} | ||
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OSAL_IRQ_HANDLER(STM32_ADC1_HANDLER) | ||
{ | ||
OSAL_IRQ_PROLOGUE(); | ||
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adc_interrupt(ADC1); | ||
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OSAL_IRQ_EPILOGUE(); | ||
} |
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