FPGA: fixing GPIO input signal

timosmd · Apr 23, 2017 · a8dfda0 · a8dfda0
1 parent b190be3
commit a8dfda0
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/fpga/prj/mercury/rtl/red_pitaya_top.sv b/fpga/prj/mercury/rtl/red_pitaya_top.sv
@@ -318,6 +318,7 @@ DTL exp_t;
 IOBUF iobuf_exp_p [16-1:0] (.O(exp_i), .IO({exp_n_io, exp_p_io}), .I(exp_o), .T(exp_t));
 
 // multiplexing GPIO signals from PS with logic generator
+assign gpio.i[23:8] = exp_i;
 assign exp_o = gpio.o[23:8];
 assign exp_t = gpio.t[23:8];