Fix timer + timer testbenches #304
Merged
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
dehanj
force-pushed
the
fix-timer
branch
5 times, most recently
from
798b26d to
cabff02
Compare
|
Updated documentation, rebased on main. |
dehanj
force-pushed
the
fix-timer
branch
2 times, most recently
from
26dfa4c to
14f89e6
Compare
agren
force-pushed
the
fix-timer
branch
2 times, most recently
from
462ff43 to
9f0e073
Compare
agren
approved these changes
Nov 26, 2024
Remove redundant timer state. This fixes a bug where the timer misses a clock cycle every time the prescaler counter reaches 1. This means if one uses a large prescaler, like 18E6, it is barely noticeable, but if one have a low prescaler and a high timer value it becomes significant. This also yields the running_* registers redundant, which are removed. Add clarity to the readme. Update the timer to default to values of one, for prescaler and timer count.
- Compare against an expected result and count errors - Exit with the right error code - Lower write_word() to 1 clk cycle instead of two. It only requires one clock cycle to write, otherwise if it is two one have to compensate for it in the tests since we are counting cycles.
- Compare against an expected result and count errors - Exit with the right error code - Clean up the output
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Description
Fix a bug in the timer core, where it misses clock cycles. It is fixed by removing a redundant timer state.
The clock cycle misses every time the prescaler counter reaches 1. This means if one uses a large prescaler, like 18E6, it is barely noticeable, but if one have a low prescaler and a high timer value it becomes significant.
Hardware timers are, according to me, usually a function of:
f_time = f_freq / (prescaler * period)Our
periodus ourtimerregister.So the prescaler is used to divide the system clock to yield a timer with a wanted time for each tick.
To exemplify the issue:
If I use above and want the ticks in microseconds and I want the timer to expire after 1 millisecond.
I use 18 Mhz frequency as an example.
1 ms = 18 * 10^6 / ( 18 * 1000 ).
This means it needs 18 000 CPU clock ticks for 1 ms.
Using our testbench our timer counts 19000. Meaning our current implementation is
f_time = f_freq / ((prescaler+1) * period)Meaning a prescaler of 18 yields a timer frequency of 0.947 MHz instead of 1 Mhz.
This PR also fixes the testbenches, so it actually test against an expected value and makes them selftesting.
This also lowers the LC utilization with about 75 LCs.
I have not updated the digest of the bitstream yet, I will do it as soon as no feedback yields a change in the code.
Fixes # (issues)
Type of change
Submission checklist