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Add files and functionality to simulate an app on the top level. #303

Merged
merged 11 commits into from
Nov 28, 2024
Merged

Add files and functionality to simulate an app on the top level. #303

merged 11 commits into from
Nov 28, 2024
+772 −218

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jthornblad
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Description

Add files and functionality to simulate an app on the top level of appliaction FPGA.

Type of change

Please tick any that are relevant to this PR and remove any that aren't.

  • Bugfix (non breaking change which resolve an issue)
  • Feature (non breaking change which adds functionality)
  • Breaking Change (a change which would cause existing functionality to not work as expected)
  • Documentation (a change to documentation)

Submission checklist

  • My code follows the style guidelines of this project
  • I have performed a self-review of my changes
  • I have tested and verified my changes on target
  • My changes are well written and CI is passing
  • I have squashed my work to relevant commits and rebased on main for linear history
  • I have added a "Co-authored-by: x" if several people contributed, either pair programming or by squashing commits from different authors.
  • I have updated the documentation where relevant (readme, dev.tillitis.se etc.)
  • QEMU is updated to reflect changes

Sorry, something went wrong.

@jthornblad jthornblad force-pushed the add_top_level_simulation branch from eaf9ea5 to 4a28ea3 Compare November 25, 2024 16:06
@jthornblad jthornblad marked this pull request as ready for review November 26, 2024 09:19
dehanj
dehanj reviewed Nov 26, 2024
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@dehanj dehanj left a comment

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Not finished with my review, but this is a start.
Will continue tomorrow.

dehanj
dehanj reviewed Nov 27, 2024
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In general works great, looks good.

I few things:

  • In the Makefile under the make help target, the tb_application_fpga target is missing
  • See the rest of the comments

@dehanj dehanj force-pushed the add_top_level_simulation branch 2 times, most recently from d235404 to 0bc1206 Compare November 27, 2024 17:12
jthornblad and others added 11 commits November 28, 2024 16:09
@jthornblad @dehanj
Add APP_SIZE parameter to tk1 block to set size of application when s…
e54045a 
…imulating.
@jthornblad @dehanj
Align module name with its file name.
d3b9660
@jthornblad @dehanj
Add verilog file for TRNG simulation
a330aa1
@jthornblad @dehanj
Update application_fpga_sim.v to match application_fpga.v
4260e1d
@jthornblad @dehanj
Add top level testbench for application_fpga_sim.v
3cd902f
@jthornblad @agren @dehanj
Add script to split app into simulation ram
fe9055e 
Co-authored-by: Mikael Ågren <mikael@tillitis.se>
@jthornblad @dehanj
Add needed changes to firmware for simulation.
15ce2c4
@jthornblad @dehanj
Remove non-working make targets for "post-synthesis functional simula…
a99e69f 
…tion"

and "post-place and route functional simulation".
@jthornblad @dehanj
Set APP_SIZE if not defined.
48c9709
@jthornblad @dehanj
Updated application_fpga_verilator.cc to match module application_fpg…
ede92af 
…a_sim.

- include printout of used clock and baud rate speed
- Use the the same clock frequency as target
@jthornblad @dehanj
Add make target for testbench simulation and simulation firmware.
07dec8b 
Create separate sources for FPGA specific code, testbench simulation
specific code, verilator simulation specific code.
@dehanj dehanj force-pushed the add_top_level_simulation branch from 0bc1206 to 07dec8b Compare November 28, 2024 15:10
@dehanj dehanj merged commit 07dec8b into main Nov 28, 2024
5 checks passed
@dehanj dehanj deleted the add_top_level_simulation branch November 28, 2024 15:15
@dehanj dehanj linked an issue Dec 9, 2024 that may be closed by this pull request
Debug Verilator simulation #127
Closed
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@dehanj dehanj

@agren agren

@mchack-work mchack-work

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Debug Verilator simulation
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@jthornblad @dehanj