Change filename personalize.py to patch_uds_udi.py

Also adding a more detailed explaination of what the script intends to
do

hw/application_fpga/Makefile

@@ -243,7 +243,7 @@ application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE)
 		--pcf $(P)/data/$(PIN_FILE) --write $@
 
 application_fpga.asc: application_fpga_par.json $(P)/data/uds.hex $(P)/data/udi.hex
-	UDS_HEX="$(P)/data/uds.hex" UDI_HEX="$(P)/data/udi.hex" OUT_ASC=$@ $(NEXTPNR_PATH)nextpnr-ice40 --up5k --package sg48 --ignore-loops --json $< --run tools/personalize.py
+	UDS_HEX="$(P)/data/uds.hex" UDI_HEX="$(P)/data/udi.hex" OUT_ASC=$@ $(NEXTPNR_PATH)nextpnr-ice40 --up5k --package sg48 --ignore-loops --json $< --run tools/patch_uds_udi.py
 
 application_fpga.bin: application_fpga.asc bram_fw.hex firmware.hex
 	$(ICESTORM_PATH)icebram -v bram_fw.hex firmware.hex < $< > $<.tmp

hw/application_fpga/tools/personalize.py → hw/application_fpga/tools/patch_uds_udi.py

@@ -1,13 +1,25 @@
 # -*- coding: utf-8 -*-
 #=======================================================================
 #
-# personalize.py
+# patch_uds_udi.py
 # --------------
 # Python program that patches the UDS and UDI implemented using
 # named LUT4 instances to have unique initial values, not the generic
 # values used during synthesis, p&r and mapping. This allows us to
 # generate device unique bitstreams without running the complete flow.
 #
+# Both the UDI and UDS are using bit indexing from 32 LUTs for each
+# word, i.e., the first word consists of bit 0 from each 32 LUTs and
+# so on. The size requirements for the UDI and UDS are specified as 1
+# bit (8 bytes of data) and 3 bits (32 bytes of data), respectively.
+# The UDI does not occupie the entire LUT4 instance, and to conserve
+# resources, the pattern of the UDI is repeated over the unused
+# portion of the LUT4 instance. This eliminates the need to drive the
+# three MSB pins while still achieving the correct output. In the case
+# of UDS, a read-enable signal is present, and the most significant
+# bit serves as the read-enable input. This requires the lower half of
+# initialization bits to be forced to zero, ensuring that the memory
+# outputs zero when the read-enable signal is inactive.
 #
 # Copyright (C) 2023 Tillitis AB
 # Written by Myrtle Shah <[email protected]>